{"id":3700135,"url":"https://alion.io/job/amd-advanced-substrate-design-process-integration-2","title":"Advanced Substrate Design & Process Integration","company":{"id":93,"name":"AMD","domain":"amd.com","url":"https://alion.io/company/amd","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Jibe","truth_index":{"grade":"A","score":92,"open_postings":16,"ghost_share":0,"stale_share":0.125,"repost_share":0,"time_to_fill_p50_days":61,"computed_at":"2026-11-05T05:54:30Z"}},"role":"Semiconductors","role_family":"Semiconductors","seniority":null,"employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Austin, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":true,"relocation_package":false,"has_equity":false,"technologies":[{"name":"HPC","optional":false}],"status":"live","first_seen_at":"2026-11-03T17:42:00Z","employer_posted_date":"2026-11-03","last_verified_at":"2026-11-05T15:04:49Z","board_verified":true,"closed_at":null,"days_open":1,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":1},"description":"ADVANCE YOUR CAREER. ADVANCE THE WORLD.\nAt AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.\nWhether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Join us and, together, we’ll advance your career.\nTHE ROLE\nLead the development of next-generation substrate architecture, design rules, and technology platforms that enable AMD's future packaging solutions. This role focuses on substrate design enablement, process integration, design-for-manufacturability (DFM), design-for-yield (DFY), reliability, and electrical performance optimization. This role is for a seasoned engineer todefine substrate technology requirements and design methodologies that bridge product needs with manufacturing capabilities. You will work closely with package architects, substrate designers, silicon teams, and manufacturing partners to co-optimize substrate solutions for performance, yield, reliability, and cost.\nTHE PERSON\nThe ideal candidate is a technical leader with deep expertise in substrate design architecture, process integration, substrate manufacturing technologies, and package-system co-design. They have developed substrate design rules and technology platforms used in advanced semiconductor products. They understand the tradeoffs between electrical performance, mechanical reliability, manufacturability, and cost, and are skilled at translating product requirements into scalable substrate technologies.\nKEY RESPONSIBILITIES\nSubstrate Architecture & Design Rule Development\nDefine substrate technology requirements and design roadmaps for future AMD products.\nDevelop substrate design rules, stack-up methodologies, routing architectures, and technology guidelines.\nEstablish scalable design infrastructures supporting future substrate technology nodes.\nDrive substrate architecture development across line/space scaling, via technologies, and advanced package integration.\nProcess Integration\nLead design-process co-optimization activities across substrate manufacturing technologies.\nDefine process-aware design methodologies that improve manufacturability and reduce development risk.\nCollaborate with suppliers to establish process windows, design limitations, and technology capabilities.\nDrive technology readiness assessments for emerging substrate platforms.\nDesign for Yield (DFY)\nDevelop design methodologies that maximize manufacturing yield and process robustness.\nIdentify systematic design sensitivities impacting supplier yield and manufacturing cost.\nDefine design guidelines and best practices that improve technology scalability.\nDrive design-related yield learning and continuous improvement initiatives.\nReliability Engineering\nLead substrate reliability strategy and design rule development for mechanical and electrical robustness.\nDevelop reliability-aware design guidelines for advanced package applications.\nPartner with reliability teams to understand failure mechanisms and translate learning into improved design requirements.\nDrive technology qualification and design robustness assessments.\nPerformance Optimization\nDrive substrate architecture solutions for signal integrity, power integrity, and high-speed package performance.\nCollaborate with package and silicon architects to optimize electrical performance across the package system.\nDevelop technology solutions supporting future AI, HPC, and heterogeneous integration products.\nBalance performance requirements with manufacturability, reliability, and cost objectives.\nSupplier Technology Leadership\nInfluence substrate supplier technology roadmaps and capability development.\nEvaluate emerging substrate technologies and manufacturing innovations.\nEstablish design requirements and technical targets for development partners.\nBuild strategic technology partnerships across the substrate ecosystem.PREFERRED EXPERIENCE\n\nExperience in advanced packaging, substrate design, or package technology development.\nDeep expertise in substrate stack-up architecture, routing technologies, HDI design, and advanced package substrates.\nExtensive experience developing substrate design rules for manufacturing and reliability.\nStrong understanding of signal integrity, power integrity, and package electrical performance.\nExperience with design-for-manufacturability, design-for-yield, and design-process co-optimization.\nStrong understanding of substrate manufacturing processes and process integration principles.\nExperience supporting advanced package architectures including chiplet, 2.5D, and heterogeneous integration solutions.\nProven ability to influence technical direction across multiple organizations and suppliers.\nDemonstrated success presenting strategy and technical roadmaps to senior leadership.\nThis role is not eligible for visa sponsorship\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.\nTHE ROLE\nLead the development of next-generation substrate architecture, design rules, and technology platforms that enable AMD's future packaging solutions. This role focuses on substrate design enablement, process integration, design-for-manufacturability (DFM), design-for-yield (DFY), reliability, and electrical performance optimization. This role is for a seasoned engineer todefine substrate technology requirements and design methodologies that bridge product needs with manufacturing capabilities. You will work closely with package architects, substrate designers, silicon teams, and manufacturing partners to co-optimize substrate solutions for performance, yield, reliability, and cost.\nTHE PERSON\nThe ideal candidate is a technical leader with deep expertise in substrate design architecture, process integration, substrate manufacturing technologies, and package-system co-design. They have developed substrate design rules and technology platforms used in advanced semiconductor products. They understand the tradeoffs between electrical performance, mechanical reliability, manufacturability, and cost, and are skilled at translating product requirements into scalable substrate technologies.\nKEY RESPONSIBILITIES\nSubstrate Architecture & Design Rule Development\nDefine substrate technology requirements and design roadmaps for future AMD products.\nDevelop substrate design rules, stack-up methodologies, routing architectures, and technology guidelines.\nEstablish scalable design infrastructures supporting future substrate technology nodes.\nDrive substrate architecture development across line/space scaling, via technologies, and advanced package integration.\nProcess Integration\nLead design-process co-optimization activities across substrate manufacturing technologies.\nDefine process-aware design methodologies that improve manufacturability and reduce development risk.\nCollaborate with suppliers to establish process windows, design limitations, and technology capabilities.\nDrive technology readiness assessments for emerging substrate platforms.\nDesign for Yield (DFY)\nDevelop design methodologies that maximize manufacturing yield and process robustness.\nIdentify systematic design sensitivities impacting supplier yield and manufacturing cost.\nDefine design guidelines and best practices that improve technology scalability.\nDrive design-related yield learning and continuous improvement initiatives.\nReliability Engineering\nLead substrate reliability strategy and design rule development for mechanical and electrical robustness.\nDevelop reliability-aware design guidelines for advanced package applications.\nPartner with reliability teams to understand failure mechanisms and translate learning into improved design requirements.\nDrive technology qualification and design robustness assessments.\nPerformance Optimization\nDrive substrate architecture solutions for signal integrity, power integrity, and high-speed package performance.\nCollaborate with package and silicon architects to optimize electrical performance across the package system.\nDevelop technology solutions supporting future AI, HPC, and heterogeneous integration products.\nBalance performance requirements with manufacturability, reliability, and cost objectives.\nSupplier Technology Leadership\nInfluence substrate supplier technology roadmaps and capability development.\nEvaluate emerging substrate technologies and manufacturing innovations.\nEstablish design requirements and technical targets for development partners.\nBuild strategic technology partnerships across the substrate ecosystem.PREFERRED EXPERIENCE\n\nExperience in advanced packaging, substrate design, or package technology development.\nDeep expertise in substrate stack-up architecture, routing technologies, HDI design, and advanced package substrates.\nExtensive experience developing substrate design rules for manufacturing and reliability.\nStrong understanding of signal integrity, power integrity, and package electrical performance.\nExperience with design-for-manufacturability, design-for-yield, and design-process co-optimization.\nStrong understanding of substrate manufacturing processes and process integration principles.\nExperience supporting advanced package architectures including chiplet, 2.5D, and heterogeneous integration solutions.\nProven ability to influence technical direction across multiple organizations and suppliers.\nDemonstrated success presenting strategy and technical roadmaps to senior leadership.\nThis role is not eligible for visa sponsorship\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.","description_format":"text","description_chars":11544,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Computer Components","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-11-03T19:13:57Z"}],"visa":[],"liveness":{"score":90,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.903,"p_room":1,"age_days":1,"expected_fill_days":61,"reasons":["conf:2","velocity","win:early","comp:brand"],"computed_at":"2026-11-05T05:54:30Z"},"pay":null,"html_url":"https://alion.io/job/amd-advanced-substrate-design-process-integration-2","json_url":"https://alion.io/job/amd-advanced-substrate-design-process-integration-2.json","meta":{"generated_at":"2026-11-05T17:08:36Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":22504,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-06T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":93},"rest":"https://alion.io/mcp/rest/get_company?id=93"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Famd-advanced-substrate-design-process-integration-2"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Famd-advanced-substrate-design-process-integration-2"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Famd-advanced-substrate-design-process-integration-2"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/amd-advanced-substrate-design-process-integration-2\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Famd-advanced-substrate-design-process-integration-2"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":3700135}},{"tool":"search_jobs","arguments":{"company":"amd.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":3700135},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. Docs: https://alion.io/developers"}}