{"id":2912238,"url":"https://alion.io/job/amd-asic-design-engineer-networking-dpu-ai-systems","title":"ASIC Design Engineer - Networking/ DPU/ AI Systems","company":{"id":93,"name":"AMD","domain":"amd.com","url":"https://alion.io/company/amd","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Jibe","truth_index":{"grade":"A","score":99,"open_postings":65,"ghost_share":0,"stale_share":0.031,"repost_share":0,"time_to_fill_p50_days":53,"computed_at":"2026-11-03T05:54:40Z"}},"role":"Hardware","role_family":"Hardware","seniority":null,"employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Santa Clara, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":131000,"max_usd":297000,"period":"year","method":"role_country_seniority_unknown","sample_n":3123},"experience_years_min":null,"visa_sponsorship":true,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false}],"status":"closed","first_seen_at":"2026-05-26T21:01:00Z","employer_posted_date":"2026-11-03","last_verified_at":"2026-11-03T14:31:17Z","board_verified":false,"closed_at":"2026-11-03T14:31:17Z","days_open":160,"trust":{"level":"stale","repost_count":0,"flags":["stale"],"days_open":158},"description":"WHAT YOU DO AT AMD CHANGES EVERYTHING\nAt AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gamingand embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuityand a shared passion to create something extraordinary. When you join AMD, you’lldiscover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.Together, we advance your career.\nTHE TEAM:\nOur group, NTSG, develops advanced system solutions that combine ASIC, hardware, and software to enable next-generation AI networking workloads. We are building highly integrated, high-performance networking systems and are looking for experienced ASIC engineers to help drive development from architecture through production.\nTHE ROLE:\nWe are seeking a Senior ASIC Design Engineer with seasoned experience in the development of high-speed, complex ASICs. The ideal candidate has hands-on experience across the full ASIC development cycle - from RTL architecture and design through tapeout, silicon bring-up, and mass production.\nTHE PERSON:\nWe are seeking a Senior ASIC Design Engineer with seasoned experience in the development of high-speed, complex ASICs. The ideal candidate has hands-on experience across the full ASIC development cycle - from RTL architecture and design through tapeout, silicon bring-up, and mass production.\nKEY RESPONSIBILITIES:\nArchitect and design key blocks for next-generation DPU ASICs targeting AI networking workloads\nContribute across the full ASIC development lifecyclearchitecture definition\nmicroarchitecture and RTL design\ndesign reviews\nimplementation support\ntapeout\nsilicon bring-up\nproduction ramp and mass deployment support\n\nCollaborate on advanced network processing engines, including P4-based, protocol-independent packet processing solutions\nDesign and implement high-speed, complex ASIC blocks for networking and data movement applications\nWork closely with verification, modeling, software, and hardware teams to ensure functional correctness and system-level performance\nDebug and resolve issues across simulation, emulation, lab bring-up, and post-silicon phases\nContribute to performance, power, and area optimization\nSupport integration of ASIC IPs into larger SoC and system architectures\nProduce high-quality design documentation and participate in technical reviews\nREQUIRED QUALIFICATIONS:\nSeasoned ASIC design experience\nProven hands-on experience developing high-speed, complex ASICs\nStrong experience across the complete ASIC development cycle, from RTL architecture to tapeout to mass production\nSolid background in networking and packet-processing architectures\nExperience collaborating across:Verification\nModeling\nSoftware\nHardware/system teams\n\nStrong RTL design skills in:\nVerilog\nSystemVerilog\n\nStrong programming skills in:C/C++\n\nScripting experience in:Python\nTcl\nShell\n\nPREFERRED QUALIFICATIONS:\nExperience designing complex ARM- or RISC-V-based SoC ASICs\nHands-on experience building complex Network-on-Chip (NoC) architectures\nStrong knowledge of AXI / AMBA protocols\nFamiliarity with P4, programmable packet-processing pipelines, or protocol-independent networking architectures\nExperience with post-silicon debug, bring-up, and production support\nExperience with high-performance interconnect, data movement, and SoC integration\nSelf-motivated engineer with strong ownership and execution skills\nStrong problem-solving ability and willingness to take on new technical challenges\nContinuous learner who thrives in a fast-moving environment\nExcellent communication and cross-functional collaboration skills\nACADEMIC CREDENTIALS:\nBachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field\nLOCATION:\nSanta Clara, CA\n#LI-NP1\nThis role is not eligible for visa sponsorship.\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.\nTHE TEAM:\nOur group, NTSG, develops advanced system solutions that combine ASIC, hardware, and software to enable next-generation AI networking workloads. We are building highly integrated, high-performance networking systems and are looking for experienced ASIC engineers to help drive development from architecture through production.\nTHE ROLE:\nWe are seeking a Senior ASIC Design Engineer with seasoned experience in the development of high-speed, complex ASICs. The ideal candidate has hands-on experience across the full ASIC development cycle - from RTL architecture and design through tapeout, silicon bring-up, and mass production.\nTHE PERSON:\nWe are seeking a Senior ASIC Design Engineer with seasoned experience in the development of high-speed, complex ASICs. The ideal candidate has hands-on experience across the full ASIC development cycle - from RTL architecture and design through tapeout, silicon bring-up, and mass production.\nKEY RESPONSIBILITIES:\nArchitect and design key blocks for next-generation DPU ASICs targeting AI networking workloads\nContribute across the full ASIC development lifecyclearchitecture definition\nmicroarchitecture and RTL design\ndesign reviews\nimplementation support\ntapeout\nsilicon bring-up\nproduction ramp and mass deployment support\n\nCollaborate on advanced network processing engines, including P4-based, protocol-independent packet processing solutions\nDesign and implement high-speed, complex ASIC blocks for networking and data movement applications\nWork closely with verification, modeling, software, and hardware teams to ensure functional correctness and system-level performance\nDebug and resolve issues across simulation, emulation, lab bring-up, and post-silicon phases\nContribute to performance, power, and area optimization\nSupport integration of ASIC IPs into larger SoC and system architectures\nProduce high-quality design documentation and participate in technical reviews\nREQUIRED QUALIFICATIONS:\nSeasoned ASIC design experience\nProven hands-on experience developing high-speed, complex ASICs\nStrong experience across the complete ASIC development cycle, from RTL architecture to tapeout to mass production\nSolid background in networking and packet-processing architectures\nExperience collaborating across:Verification\nModeling\nSoftware\nHardware/system teams\n\nStrong RTL design skills in:\nVerilog\nSystemVerilog\n\nStrong programming skills in:C/C++\n\nScripting experience in:Python\nTcl\nShell\n\nPREFERRED QUALIFICATIONS:\nExperience designing complex ARM- or RISC-V-based SoC ASICs\nHands-on experience building complex Network-on-Chip (NoC) architectures\nStrong knowledge of AXI / AMBA protocols\nFamiliarity with P4, programmable packet-processing pipelines, or protocol-independent networking architectures\nExperience with post-silicon debug, bring-up, and production support\nExperience with high-performance interconnect, data movement, and SoC integration\nSelf-motivated engineer with strong ownership and execution skills\nStrong problem-solving ability and willingness to take on new technical challenges\nContinuous learner who thrives in a fast-moving environment\nExcellent communication and cross-functional collaboration skills\nACADEMIC CREDENTIALS:\nBachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field\nLOCATION:\nSanta Clara, CA\n#LI-NP1\nThis role is not eligible for visa sponsorship.\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.","description_format":"text","description_chars":9425,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Artificial Intelligence","Processors, MCUs & AI Chips","Computer Components","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-10-20T09:52:16Z"},{"event":"close","at":"2026-10-31T02:11:15Z"},{"event":"reopen","at":"2026-10-31T06:09:31Z"},{"event":"close","at":"2026-10-31T09:50:42Z"},{"event":"reopen","at":"2026-10-31T20:55:29Z"},{"event":"close","at":"2026-11-01T10:01:16Z"},{"event":"reopen","at":"2026-11-01T14:06:37Z"},{"event":"close","at":"2026-11-02T00:03:04Z"},{"event":"reopen","at":"2026-11-02T09:29:27Z"},{"event":"close","at":"2026-11-02T16:06:30Z"},{"event":"reopen","at":"2026-11-03T06:59:51Z"},{"event":"close","at":"2026-11-03T14:31:17Z"}],"visa":[],"liveness":null,"pay":null,"html_url":"https://alion.io/job/amd-asic-design-engineer-networking-dpu-ai-systems","json_url":"https://alion.io/job/amd-asic-design-engineer-networking-dpu-ai-systems.json","meta":{"generated_at":"2026-11-03T22:07:06Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":495,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-04T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":93},"rest":"https://alion.io/mcp/rest/get_company?id=93"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Famd-asic-design-engineer-networking-dpu-ai-systems"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Famd-asic-design-engineer-networking-dpu-ai-systems"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Famd-asic-design-engineer-networking-dpu-ai-systems"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/amd-asic-design-engineer-networking-dpu-ai-systems\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Famd-asic-design-engineer-networking-dpu-ai-systems"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":2912238}},{"tool":"search_jobs","arguments":{"company":"amd.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":2912238},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. 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