{"id":3035356,"url":"https://alion.io/job/amd-asic-design-engineer-pcie-ip-enablement","title":"ASIC Design Engineer, PCIe IP Enablement","company":{"id":93,"name":"AMD","domain":"amd.com","url":"https://alion.io/company/amd","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Jibe","truth_index":{"grade":"B","score":75,"open_postings":163,"ghost_share":0,"stale_share":0.994,"repost_share":0,"time_to_fill_p50_days":28,"computed_at":"2026-10-24T06:02:35Z"}},"role":"Hardware","role_family":"Hardware","seniority":null,"employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Markham, Canada"],"countries":["CA"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":65000,"max_usd":130000,"period":"year","method":"role_country_seniority_unknown","sample_n":146},"experience_years_min":null,"visa_sponsorship":true,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Verilog","optional":true}],"status":"live","first_seen_at":"2026-10-21T18:23:00Z","employer_posted_date":"2026-10-21","last_verified_at":"2026-10-24T02:30:27Z","board_verified":true,"closed_at":null,"days_open":2,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":2},"description":"ADVANCE YOUR CAREER. ADVANCE THE WORLD.\nAt AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.\nWhether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Join us and, together, we’ll advance your career.\n THE ROLE:\nWe are seeking a highly motivated ASIC Design Engineer, PCIe IP Enablement to join our team. In this role, you will contribute to the design and development of cutting-edge PCIe solutions, focusing on architecture, IP design, RTL implementation, and front-to-back design flows. You will collaborate closely with cross-functional teams to ensure high-quality, power-efficient, and performance-optimized designs.\nTHE PERSON:\nA successful candidate will have ASICS hardware design experience with proven end-to-end ownership of complex digital IP/subsystems from architecture through tape-out. The candidate will be highly accurate and detail-oriented, with strong communication and problem-solving skills, and will help set design development direction and mentor other engineers on the team.\nKEY RESPONSIBILITIES:\nIntegration and Implementation of the AMDs PCI Express (PCIe) subsystem, IP deployment to SoC.\nSynthesis, timing, lint and cdc closure to ensure high quality design. \nResponsible to implement the design related to test, debug, clocks.\nUnderstanding of low power design techniques and have good knowledge of the UPF based power-aware flow.\nIdentify complex technical problems, break them down, summarize multiple possible solutions, and lead the team in the right direction.\nDrive and hands-on flow development, automation, and scripting.\nWork collaboratively across teams of IP designers, Physical Design team and SoC level leads.\nTechnical and schedule discussion with multi-site engineers and managers \nPREFERRED EXPERIENCE:\nStrong understanding of Digital Design in RTL, Verilog HDL\nExperience with synthesis, linting / CDC tools, equivalence checks\nKnowledge of power saving techniques, including UPF/CPF based power-aware flows and checks.\nExperience with design flows, version control systems, integration and implementation of IPs to SoC.\n\nProficiency with RTL quality flows: Lint, CDC/RDC, synthesis, LEC, and STA\nStrong AI knowledge and experience in it's usage to develop skills and agents.\nFamiliarity with subsystem integration (tile flow, repeaters, SRAM generation, ECO) and DFx awareness (DFT / DFD)\nExcellent problem-solving and debugging skills\nACADEMIC CREDENTIALS:\nBachelor's or Master's degree in Electrical Engineering / Computer Engineering preferred\nThis role is not eligible for Visa sponsorship.\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.\nTHE ROLE:\nWe are seeking a highly motivated ASIC Design Engineer, PCIe IP Enablement to join our team. In this role, you will contribute to the design and development of cutting-edge PCIe solutions, focusing on architecture, IP design, RTL implementation, and front-to-back design flows. You will collaborate closely with cross-functional teams to ensure high-quality, power-efficient, and performance-optimized designs.\nTHE PERSON:\nA successful candidate will have ASICS hardware design experience with proven end-to-end ownership of complex digital IP/subsystems from architecture through tape-out. The candidate will be highly accurate and detail-oriented, with strong communication and problem-solving skills, and will help set design development direction and mentor other engineers on the team.\nKEY RESPONSIBILITIES:\nIntegration and Implementation of the AMDs PCI Express (PCIe) subsystem, IP deployment to SoC.\nSynthesis, timing, lint and cdc closure to ensure high quality design. \nResponsible to implement the design related to test, debug, clocks.\nUnderstanding of low power design techniques and have good knowledge of the UPF based power-aware flow.\nIdentify complex technical problems, break them down, summarize multiple possible solutions, and lead the team in the right direction.\nDrive and hands-on flow development, automation, and scripting.\nWork collaboratively across teams of IP designers, Physical Design team and SoC level leads.\nTechnical and schedule discussion with multi-site engineers and managers \nPREFERRED EXPERIENCE:\nStrong understanding of Digital Design in RTL, Verilog HDL\nExperience with synthesis, linting / CDC tools, equivalence checks\nKnowledge of power saving techniques, including UPF/CPF based power-aware flows and checks.\nExperience with design flows, version control systems, integration and implementation of IPs to SoC.\n\nProficiency with RTL quality flows: Lint, CDC/RDC, synthesis, LEC, and STA\nStrong AI knowledge and experience in it's usage to develop skills and agents.\nFamiliarity with subsystem integration (tile flow, repeaters, SRAM generation, ECO) and DFx awareness (DFT / DFD)\nExcellent problem-solving and debugging skills\nACADEMIC CREDENTIALS:\nBachelor's or Master's degree in Electrical Engineering / Computer Engineering preferred\nThis role is not eligible for Visa sponsorship.\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.","description_format":"text","description_chars":7149,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":true},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Computer Components","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-10-21T21:15:51Z"}],"visa":[],"liveness":{"score":63,"band":"ok","label":"Likely open","p_open":1,"p_active":0.632,"p_room":1,"age_days":2,"expected_fill_days":28,"reasons":["conf:3","stale_co","velocity","win:early","comp:brand"],"computed_at":"2026-10-24T06:02:35Z"},"pay":null,"html_url":"https://alion.io/job/amd-asic-design-engineer-pcie-ip-enablement","json_url":"https://alion.io/job/amd-asic-design-engineer-pcie-ip-enablement.json","meta":{"generated_at":"2026-10-24T06:24:03Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":9246,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-25T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":93},"rest":"https://alion.io/mcp/rest/get_company?id=93"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Famd-asic-design-engineer-pcie-ip-enablement"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Famd-asic-design-engineer-pcie-ip-enablement"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Famd-asic-design-engineer-pcie-ip-enablement"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/amd-asic-design-engineer-pcie-ip-enablement\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Famd-asic-design-engineer-pcie-ip-enablement"}]}