{"id":2912262,"url":"https://alion.io/job/amd-asic-design-sta-engineer","title":"ASIC Design STA Engineer","company":{"id":93,"name":"AMD","domain":"amd.com","url":"https://alion.io/company/amd","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Jibe","truth_index":{"grade":"B","score":75,"open_postings":162,"ghost_share":0,"stale_share":0.994,"repost_share":0,"time_to_fill_p50_days":29,"computed_at":"2026-10-26T05:57:25Z"}},"role":"Hardware","role_family":"Hardware","seniority":null,"employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["San Jose, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":131000,"max_usd":297000,"period":"year","method":"role_country_seniority_unknown","sample_n":3123},"experience_years_min":null,"visa_sponsorship":true,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Linux","optional":false},{"name":"Synopsys Design Compiler","optional":false},{"name":"Synopsys PrimeTime","optional":false},{"name":"Synopsys SpyGlass","optional":true}],"status":"live","first_seen_at":"2026-04-17T22:25:00Z","employer_posted_date":"2026-10-20","last_verified_at":"2026-10-27T00:07:26Z","board_verified":true,"closed_at":null,"days_open":192,"trust":{"level":"stale","repost_count":0,"flags":["stale"],"days_open":191},"description":"WHAT YOU DO AT AMD CHANGES EVERYTHING\nAt AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gamingand embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuityand a shared passion to create something extraordinary. When you join AMD, you’lldiscover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.Together, we advance your career.\nTHE ROLE:\nAMD is looking for an ASIC Design STA engineer to contribute to the development of large SoCs, featuring multiple physical blocks and over 300 clock domains. The candidate's responsibilities will include building and verifying timing constraints for intricate SoC designs. This role demands a combination of SDC expertise, EDA tool proficiency, and TCL-based scripting abilities. The candidate should possess extensive experience in SDC development and debugging, be familiar with enhancing various RTL quality metrics for complex, hierarchical designs, and be able to automate these processes for increased efficiency. Proficiency in both front-end (RTL) processes and back-end (Synthesis and P&R) processes is preferred.\nTHE PERSON:\nHigh energy candidates with strong written and verbal communication skills, and structured, well-organized work habits will be successful. Team and goal oriented are essential.\nKEY RESPONSIBILITIES:\nResponsible for the development of complex multi-mode / multi-corner timing constraints that are compatible for RTL and signoff\nLead the effort to maintain RTL quality metrics in complex, hierarchical designs, while automating the process for increased efficiency.\nImplement the pre-route timing checks and QoR clean up to eliminate timing constraints issues and ensure a quality handoff for STA checks.\ncollaborate with CAD on the development of pre-production synthesis (Design Compiler) and STA (Primetime) work flows.\nRequire a blend of SDC expertise, proficiency in EDA tools, and Tcl based scripting abilities (in both EDA environment and standalone Linux Tcl shell scripts)\nPREFERRED EXPERIENCE:\nWorked with EDA tools that enable RTL quality checks\nHands on experience in building the timing constraints for IPs, blocks and Full-chip implementation in both flat/hierarchical flows.\nExperience with analyzing the timing reports and identifying both the design and constraints related issues.\nAbility to multitask, grasp new flows/tools/ideas.\nExperience in improving the methodologies.\nPreferred EDA tool experience: Synopsys Design Compiler/Primetime, Spyglass, Fishtail etc.\nPrior experience developing complex TCL scripts in Synopsys Design Compiler (DC) and PrimeTime (PT)\nWriting custom TCL QC and QoR checks using DC/PT object attributes queries and filters\nStrong analytical and problem-solving skills \nACADEMIC CREDENTIALS:\nBachelors or Masters degree in computer engineering/Electrical Engineering or a related field\nLOCATION: San Jose, CA\nThis role is not eligible for visa sponsorship.\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.\nTHE ROLE:\nAMD is looking for an ASIC Design STA engineer to contribute to the development of large SoCs, featuring multiple physical blocks and over 300 clock domains. The candidate's responsibilities will include building and verifying timing constraints for intricate SoC designs. This role demands a combination of SDC expertise, EDA tool proficiency, and TCL-based scripting abilities. The candidate should possess extensive experience in SDC development and debugging, be familiar with enhancing various RTL quality metrics for complex, hierarchical designs, and be able to automate these processes for increased efficiency. Proficiency in both front-end (RTL) processes and back-end (Synthesis and P&R) processes is preferred.\nTHE PERSON:\nHigh energy candidates with strong written and verbal communication skills, and structured, well-organized work habits will be successful. Team and goal oriented are essential.\nKEY RESPONSIBILITIES:\nResponsible for the development of complex multi-mode / multi-corner timing constraints that are compatible for RTL and signoff\nLead the effort to maintain RTL quality metrics in complex, hierarchical designs, while automating the process for increased efficiency.\nImplement the pre-route timing checks and QoR clean up to eliminate timing constraints issues and ensure a quality handoff for STA checks.\ncollaborate with CAD on the development of pre-production synthesis (Design Compiler) and STA (Primetime) work flows.\nRequire a blend of SDC expertise, proficiency in EDA tools, and Tcl based scripting abilities (in both EDA environment and standalone Linux Tcl shell scripts)\nPREFERRED EXPERIENCE:\nWorked with EDA tools that enable RTL quality checks\nHands on experience in building the timing constraints for IPs, blocks and Full-chip implementation in both flat/hierarchical flows.\nExperience with analyzing the timing reports and identifying both the design and constraints related issues.\nAbility to multitask, grasp new flows/tools/ideas.\nExperience in improving the methodologies.\nPreferred EDA tool experience: Synopsys Design Compiler/Primetime, Spyglass, Fishtail etc.\nPrior experience developing complex TCL scripts in Synopsys Design Compiler (DC) and PrimeTime (PT)\nWriting custom TCL QC and QoR checks using DC/PT object attributes queries and filters\nStrong analytical and problem-solving skills \nACADEMIC CREDENTIALS:\nBachelors or Masters degree in computer engineering/Electrical Engineering or a related field\nLOCATION: San Jose, CA\nThis role is not eligible for visa sponsorship.\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.","description_format":"text","description_chars":7735,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Computer Components","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-10-20T09:52:16Z"}],"visa":[],"liveness":{"score":3,"band":"cold","label":"Long shot","p_open":1,"p_active":0.112,"p_room":0.28,"age_days":191,"expected_fill_days":29,"reasons":["conf:1","stale_co","velocity","win:tail","crowd:brand"],"computed_at":"2026-10-26T05:57:25Z"},"pay":null,"html_url":"https://alion.io/job/amd-asic-design-sta-engineer","json_url":"https://alion.io/job/amd-asic-design-sta-engineer.json","meta":{"generated_at":"2026-10-27T01:33:05Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":452,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-28T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":93},"rest":"https://alion.io/mcp/rest/get_company?id=93"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Famd-asic-design-sta-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Famd-asic-design-sta-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Famd-asic-design-sta-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/amd-asic-design-sta-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Famd-asic-design-sta-engineer"}]}