{"id":2911873,"url":"https://alion.io/job/amd-asic-design-verification-engineer","title":"ASIC Design Verification Engineer","company":{"id":93,"name":"AMD","domain":"amd.com","url":"https://alion.io/company/amd","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Jibe","truth_index":{"grade":"B","score":75,"open_postings":171,"ghost_share":0,"stale_share":0.994,"repost_share":0,"time_to_fill_p50_days":30,"computed_at":"2026-10-28T05:59:10Z"}},"role":"Hardware","role_family":"Hardware","seniority":null,"employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Rochester, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":111000,"max_usd":251000,"period":"year","method":"role_country_seniority_unknown","sample_n":3123},"experience_years_min":null,"visa_sponsorship":true,"relocation_package":false,"has_equity":false,"technologies":[{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Formal Verification","optional":true},{"name":"Verilog","optional":true}],"status":"live","first_seen_at":"2026-08-18T15:17:00Z","employer_posted_date":"2026-10-20","last_verified_at":"2026-10-28T08:32:14Z","board_verified":true,"closed_at":null,"days_open":70,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":70},"description":"ADVANCE YOUR CAREER. ADVANCE THE WORLD.\nAt AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them.\nAMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger - technology that moves the world forward.\nTHE ROLE:\nThe focus of this role is to own the verification strategy and coverage closure for AMD's mixed-signal power management IP, driving system-level verification of the full SOC while also contributing block-level verification and RTL design.\nTHE PERSON:\nYou have a passion for finding bugs. You think in terms of coverage, corner cases, and what has not been exercised yet. You are comfortable reading RTL as well as writing testbenches, and you enjoy working at the boundary between digital and analog. You are a team player with excellent communication skills, strong analytical and problem-solving ability, and the persistence to chase an intermittent failure to root cause.\nKEY RESPONSIBILITIES:\nVerification Ownership & Coverage\nOwn the overall verification strategy, test plan, and coverage closure for a mixed-signal power management IC \nDefine functional and code coverage goals, track progress against them, and report verification status and readiness to the project team \nOwn verification signoff criteria and drive the team to coverage closure ahead of tape-out \nMaintain and improve regression infrastructure, triage flow, and results reporting \nSystem-Level Verification\nDevelop and execute system-level verification of the full SOC, including boot and reset sequencing, power state transitions, fault and protection scenarios, and host interface traffic \nVerify firmware-driven behavior in co-simulation of embedded firmware with RTL \nBuild and maintain SystemVerilog/UVM testbench components, sequences, checkers, and assertions at the system level \nBlock-Level & Mixed-Signal Verification\nDevelop block-level test benches and coverage for digital blocks as project needs require \nVerify digital/analog interfaces using real-number models (RNM) of analog macros, including model bring-up, correlation to analog behavior, and debug in the digital simulation environment \nPartner with Analog Design and RTL Design to review model fidelity and ensure the verified behavior matches silicon intent \nCollaboration & Design Support\nPartner with RTL designers on design reviews, verification planning, and debug of failures to root cause \nContribute to SystemVerilog RTL design work across the team as needed \nSupport post-silicon bring-up, including correlation of silicon behavior back to pre-silicon test cases \nWork across Analog, Firmware, Systems Engineering, and Architecture teams; mentor junior engineers on verification methodology \nPREFERRED QUALIFICATIONS:\nSystem-level or SOC-level verification ownership on a mixed-signal device \nReal-number modeling (RNM) of analog blocks in SystemVerilog (wreal / nettype real), or experience with Verilog-AMS \nSystemVerilog RTL design experience in an ASIC environment \nFirmware/RTL co-simulation or hardware/software co-verification experience \nFormal verification, assertion-based verification (SVA), or emulation/FPGA prototyping experience \nPost-silicon bring-up and debug experience \nExperience mentoring engineers and leading verification reviews \nStrong SystemVerilog and UVM testbench development skills, with ownership of verification for a block or subsystem through tape-out \nDemonstrated experience defining verification plans and driving functional and code coverage to closure \nProficiency with simulation, coverage, and debug tools, and with regression automation \nAbility to read and understand RTL and design specifications to independently derive test intent \nACADEMC CREDENTIALS:\nBachelors or master's in electrical/computer engineering\nThis role is not eligible for visa sponsorship.\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.\nTHE ROLE:\nThe focus of this role is to own the verification strategy and coverage closure for AMD's mixed-signal power management IP, driving system-level verification of the full SOC while also contributing block-level verification and RTL design.\nTHE PERSON:\nYou have a passion for finding bugs. You think in terms of coverage, corner cases, and what has not been exercised yet. You are comfortable reading RTL as well as writing testbenches, and you enjoy working at the boundary between digital and analog. You are a team player with excellent communication skills, strong analytical and problem-solving ability, and the persistence to chase an intermittent failure to root cause.\nKEY RESPONSIBILITIES:\nVerification Ownership & Coverage\nOwn the overall verification strategy, test plan, and coverage closure for a mixed-signal power management IC \nDefine functional and code coverage goals, track progress against them, and report verification status and readiness to the project team \nOwn verification signoff criteria and drive the team to coverage closure ahead of tape-out \nMaintain and improve regression infrastructure, triage flow, and results reporting \nSystem-Level Verification\nDevelop and execute system-level verification of the full SOC, including boot and reset sequencing, power state transitions, fault and protection scenarios, and host interface traffic \nVerify firmware-driven behavior in co-simulation of embedded firmware with RTL \nBuild and maintain SystemVerilog/UVM testbench components, sequences, checkers, and assertions at the system level \nBlock-Level & Mixed-Signal Verification\nDevelop block-level test benches and coverage for digital blocks as project needs require \nVerify digital/analog interfaces using real-number models (RNM) of analog macros, including model bring-up, correlation to analog behavior, and debug in the digital simulation environment \nPartner with Analog Design and RTL Design to review model fidelity and ensure the verified behavior matches silicon intent \nCollaboration & Design Support\nPartner with RTL designers on design reviews, verification planning, and debug of failures to root cause \nContribute to SystemVerilog RTL design work across the team as needed \nSupport post-silicon bring-up, including correlation of silicon behavior back to pre-silicon test cases \nWork across Analog, Firmware, Systems Engineering, and Architecture teams; mentor junior engineers on verification methodology \nPREFERRED QUALIFICATIONS:\nSystem-level or SOC-level verification ownership on a mixed-signal device \nReal-number modeling (RNM) of analog blocks in SystemVerilog (wreal / nettype real), or experience with Verilog-AMS \nSystemVerilog RTL design experience in an ASIC environment \nFirmware/RTL co-simulation or hardware/software co-verification experience \nFormal verification, assertion-based verification (SVA), or emulation/FPGA prototyping experience \nPost-silicon bring-up and debug experience \nExperience mentoring engineers and leading verification reviews \nStrong SystemVerilog and UVM testbench development skills, with ownership of verification for a block or subsystem through tape-out \nDemonstrated experience defining verification plans and driving functional and code coverage to closure \nProficiency with simulation, coverage, and debug tools, and with regression automation \nAbility to read and understand RTL and design specifications to independently derive test intent \nACADEMC CREDENTIALS:\nBachelors or master's in electrical/computer engineering\nThis role is not eligible for visa sponsorship.\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.","description_format":"text","description_chars":9766,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Computer Components","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-10-20T09:44:57Z"}],"visa":[],"liveness":{"score":6,"band":"cold","label":"Long shot","p_open":1,"p_active":0.222,"p_room":0.28,"age_days":70,"expected_fill_days":30,"reasons":["conf:2","stale_co","velocity","win:tail","crowd:brand"],"computed_at":"2026-10-28T05:59:10Z"},"pay":null,"html_url":"https://alion.io/job/amd-asic-design-verification-engineer","json_url":"https://alion.io/job/amd-asic-design-verification-engineer.json","meta":{"generated_at":"2026-10-28T12:30:30Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":16483,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-29T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":93},"rest":"https://alion.io/mcp/rest/get_company?id=93"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Famd-asic-design-verification-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Famd-asic-design-verification-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Famd-asic-design-verification-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/amd-asic-design-verification-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Famd-asic-design-verification-engineer"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":2911873}},{"tool":"search_jobs","arguments":{"company":"amd.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":2911873},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. 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