{"id":3599286,"url":"https://alion.io/job/amd-asic-rtl-design-verification-manager","title":"ASIC RTL Design Verification Manager","company":{"id":93,"name":"AMD","domain":"amd.com","url":"https://alion.io/company/amd","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Jibe","truth_index":{"grade":"A","score":99,"open_postings":65,"ghost_share":0,"stale_share":0.031,"repost_share":0,"time_to_fill_p50_days":53,"computed_at":"2026-11-03T05:54:40Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":17,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Assembly","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Python","optional":true}],"status":"live","first_seen_at":"2026-11-02T05:28:00Z","employer_posted_date":"2026-11-02","last_verified_at":"2026-11-04T01:47:01Z","board_verified":true,"closed_at":null,"days_open":1,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":1},"description":"ADVANCE YOUR CAREER. ADVANCE THE WORLD.\nAt AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.\nWhether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Join us and, together, we’ll advance your career.\nSENIOR MANAGER SILICON DESIGN ENGINEER\nPosition Overview\nSr Manager of ASIC RTL Design Verification is to lead the pre-silicon functional verification organization.\nHe will own the RTL verification strategy, methodology, execution, and sign-off at SoC levels. The role requires deep technical expertise in c/c++/ASM SystemVerilog/UVM-based verification, strong understanding of digital RTL and SoC architectures, and demonstrated experience building and leading high-performing verification teams.\nHe will work closely with RTL design, architecture, and program management teams to deliver high-quality, functionally correct RTL and achieve predictable tape-out schedules.\nKey Responsibilities\nRTL Verification Leadership\nOwn end-to-end RTL functional verification for ASIC/SoC programs from specification through RTL sign-off.\nDefine verification strategy, architecture, methodology, execution plans, and sign-off criteria.\nDrive verification planning and execution at full-chip SoC levels.\nEstablish clear verification milestones aligned with RTL development and tape-out schedules.\nDrive verification quality, predictability, efficiency, and reuse across semiconductor programs.\nVerification Methodology & Technical Leadership\nProvide technical leadership for C/C++/ASM/SystemVerilog/UVM-based constrained-random verification.\nGuide development of scalable and reusable testbench architectures, verification components, sequences, scoreboards, checkers, reference models, and coverage models.\nDrive coverage-based verification methodology using functional coverage, code coverage, assertions, and verification-plan closure.\nEstablish methodologies for IP-to-subsystem-to-SoC verification reuse.\nVerification Execution & Sign-Off\nOwn verification execution across multiple ASIC programs and development milestones.\nEstablish measurable RTL verification sign-off criteria.\nDrive closure of verification plans, functional coverage, code coverage, assertion coverage, and regressions. Appropriately drive verification matrix.\nOrganization & People Leadership\nBuild, lead, and develop a high-performing ASIC RTL verification organization.\nRecruit and retain verification engineers, technical leads, verification architects, and engineering managers.\nEstablish clear technical ownership and accountability across IP, subsystem, and SoC verification.\nMentor senior engineers and develop future technical and management leaders.\nCross-Functional Collaboration\nPartner closely with:\nDV teams across GEO\nSoC/System Architecture\nMicroarchitecture\nRTL Design\nIP Design and Verification teams\nCAD/EDA Infrastructure\nProgram Management\nFirmware/Software teams where required for RTL verification\nDrive alignment on specifications, verification requirements, dependencies, schedules, quality metrics, and RTL sign-off criteria.\nRequired Qualifications\nBS/MS in Electrical Engineering, Computer Engineering, Computer Science, or related discipline.\n17+ years of ASIC/SoC RTL verification experience, with significant technical and people leadership responsibility.\nProven track record leading verification of complex semiconductor products through RTL sign-off and tape-out.\nStrong understanding of clock/reset architectures, interrupts, register interfaces, memory interfaces, and power-management functionality from an RTL verification perspective.\nDemonstrated ability to lead verification across multiple projects and geographically distributed teams.\nStrong engineering judgment and ability to make data-driven RTL sign-off decisions.\nExcellent communication, organizational, and leadership skills.\nPreferred Qualifications\nExperience verifying multi-core or multi-engine SoCs with complex interconnect and memory architectures.\nExperience with protocols such as PCIe, CXL, Ethernet, DDR/LPDDR, USB, or other high-speed interfaces relevant to the product.\nExperience with X86 and ARM processor subsystems.\nExperience in ARM based and X86 based SOC.\nHas understanding of GFX/GPU based SOC.\nExperience developing reusable UVM verification IP and environments.\nExperience with low-power RTL verification, including UPF-driven simulation where applicable.\nStrong scripting and automation experience using Python or similar languages.\nExperience establishing verification methodologies and infrastructure across multiple semiconductor product generations.\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.\nSENIOR MANAGER SILICON DESIGN ENGINEER\nPosition Overview\nSr Manager of ASIC RTL Design Verification is to lead the pre-silicon functional verification organization.\nHe will own the RTL verification strategy, methodology, execution, and sign-off at SoC levels. The role requires deep technical expertise in c/c++/ASM SystemVerilog/UVM-based verification, strong understanding of digital RTL and SoC architectures, and demonstrated experience building and leading high-performing verification teams.\nHe will work closely with RTL design, architecture, and program management teams to deliver high-quality, functionally correct RTL and achieve predictable tape-out schedules.\nKey Responsibilities\nRTL Verification Leadership\nOwn end-to-end RTL functional verification for ASIC/SoC programs from specification through RTL sign-off.\nDefine verification strategy, architecture, methodology, execution plans, and sign-off criteria.\nDrive verification planning and execution at full-chip SoC levels.\nEstablish clear verification milestones aligned with RTL development and tape-out schedules.\nDrive verification quality, predictability, efficiency, and reuse across semiconductor programs.\nVerification Methodology & Technical Leadership\nProvide technical leadership for C/C++/ASM/SystemVerilog/UVM-based constrained-random verification.\nGuide development of scalable and reusable testbench architectures, verification components, sequences, scoreboards, checkers, reference models, and coverage models.\nDrive coverage-based verification methodology using functional coverage, code coverage, assertions, and verification-plan closure.\nEstablish methodologies for IP-to-subsystem-to-SoC verification reuse.\nVerification Execution & Sign-Off\nOwn verification execution across multiple ASIC programs and development milestones.\nEstablish measurable RTL verification sign-off criteria.\nDrive closure of verification plans, functional coverage, code coverage, assertion coverage, and regressions. Appropriately drive verification matrix.\nOrganization & People Leadership\nBuild, lead, and develop a high-performing ASIC RTL verification organization.\nRecruit and retain verification engineers, technical leads, verification architects, and engineering managers.\nEstablish clear technical ownership and accountability across IP, subsystem, and SoC verification.\nMentor senior engineers and develop future technical and management leaders.\nCross-Functional Collaboration\nPartner closely with:\nDV teams across GEO\nSoC/System Architecture\nMicroarchitecture\nRTL Design\nIP Design and Verification teams\nCAD/EDA Infrastructure\nProgram Management\nFirmware/Software teams where required for RTL verification\nDrive alignment on specifications, verification requirements, dependencies, schedules, quality metrics, and RTL sign-off criteria.\nRequired Qualifications\nBS/MS in Electrical Engineering, Computer Engineering, Computer Science, or related discipline.\n17+ years of ASIC/SoC RTL verification experience, with significant technical and people leadership responsibility.\nProven track record leading verification of complex semiconductor products through RTL sign-off and tape-out.\nStrong understanding of clock/reset architectures, interrupts, register interfaces, memory interfaces, and power-management functionality from an RTL verification perspective.\nDemonstrated ability to lead verification across multiple projects and geographically distributed teams.\nStrong engineering judgment and ability to make data-driven RTL sign-off decisions.\nExcellent communication, organizational, and leadership skills.\nPreferred Qualifications\nExperience verifying multi-core or multi-engine SoCs with complex interconnect and memory architectures.\nExperience with protocols such as PCIe, CXL, Ethernet, DDR/LPDDR, USB, or other high-speed interfaces relevant to the product.\nExperience with X86 and ARM processor subsystems.\nExperience in ARM based and X86 based SOC.\nHas understanding of GFX/GPU based SOC.\nExperience developing reusable UVM verification IP and environments.\nExperience with low-power RTL verification, including UPF-driven simulation where applicable.\nStrong scripting and automation experience using Python or similar languages.\nExperience establishing verification methodologies and infrastructure across multiple semiconductor product generations.\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. 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