{"id":2910808,"url":"https://alion.io/job/amd-cpu-microarchitecture-cache-rtl-design-engineer","title":"CPU Microarchitecture & Cache RTL Design Engineer","company":{"id":93,"name":"AMD","domain":"amd.com","url":"https://alion.io/company/amd","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Jibe","truth_index":{"grade":"B","score":80,"open_postings":160,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":20,"computed_at":"2026-10-23T05:54:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":null,"employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Fort Collins, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":106000,"max_usd":240000,"period":"year","method":"role_country_seniority_unknown","sample_n":2844},"experience_years_min":null,"visa_sponsorship":true,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Verilog","optional":true}],"status":"live","first_seen_at":"2026-09-23T13:46:00Z","employer_posted_date":"2026-10-20","last_verified_at":"2026-10-23T13:34:26Z","board_verified":true,"closed_at":null,"days_open":30,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":30},"description":"ADVANCE YOUR CAREER. ADVANCE THE WORLD.\nAt AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.\nWhether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Join us and, together, we’ll advance your career.\nTHE ROLE:\nAMD’s Cores Organization delivers advanced CPU, Cache, and Chiplet technologies that are foundational to AMD’s server, client, and gaming products. We are seeking an experienced VLSI RTL Design Engineer to join our team as a senior technical contributor. In this role, the engineer will design and implement high-performance, energy-efficient cache and fabric solutions. This individual will contribute to the development of AMD’s next generation cores and caches while collaborating with a broad range of engineering disciplines. The engineer will join the team based in Fort Collins, CO.\nTHE PERSON:\nThe ideal candidate has experience delivering complex technical projects and achieving results within project timelines. As a Microarchitecture and RTL contributor for Cache designs, this individual enjoys collaborating with cross-functional teams that span a variety of technical disciplines.\nOur team continuously seeks innovative approaches to improve chip performance, power efficiency, and area optimization. Success in this role requires creativity, strong analytical and problem-solving skills, and effective written and verbal communication abilities. The candidate enjoys solving challenging technical problems, working collaboratively to develop solutions, and contributing to the success of multiple AMD products.\nAs the organization continues to grow in capability and scale, the candidate will have opportunities to mentor engineers, share technical expertise, and support the development of team capabilities.\nKEY RESPONSIBILITIES:\nCollaborate with Cache and CPU Architects to design, document, and execute optimized high-performance Cache and Routing Fabric designs.\nCollaborate with Physical Design teams to develop RTL optimized for physical implementation and timing closure.\nCollaborate with Design Verification teams to develop architectures and features that are clearly documented and verifiable.\nCollaborate with Design for Test teams to develop RTL that is reliable, testable, and manufacturable.\nWork across global teams to solve complex architectural interactions between IP and SoC designs.\nDevelop improvements to CPU designs by increasing quality, simplifying design complexity through innovation, and strengthening technical collaboration across teams.\nSolve complex design and tool challenges through innovative and practical solutions while contributing to technical excellence across the organization. Create technical presentations for peers and management.\nGuide and mentor other engineers.\nPREFERRED EXPERIENCE:\nPrior experience with Cache architecture development and execution, including Cache Controller and Array RTL implementation.\nPrior experience with CPU Coherency, Coherent NoC, Cache Allocation and Replacement Policy, Quality of Service, Fairness, and Forward Progress architecture and implementation.\nPrior experience collaborating effectively with diverse teams across disciplines.\nPrior experience with Digital RTL Design, Verilog HDL, and scripting.\nACADEMIC CREDENTIALS:\nBachelor’s or master’s degree in computer engineering, Electrical Engineering, or a related technical field.\nThis role is not eligible for visa sponsorship.\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.\nTHE ROLE:\nAMD’s Cores Organization delivers advanced CPU, Cache, and Chiplet technologies that are foundational to AMD’s server, client, and gaming products. We are seeking an experienced VLSI RTL Design Engineer to join our team as a senior technical contributor. In this role, the engineer will design and implement high-performance, energy-efficient cache and fabric solutions. This individual will contribute to the development of AMD’s next generation cores and caches while collaborating with a broad range of engineering disciplines. The engineer will join the team based in Fort Collins, CO.\nTHE PERSON:\nThe ideal candidate has experience delivering complex technical projects and achieving results within project timelines. As a Microarchitecture and RTL contributor for Cache designs, this individual enjoys collaborating with cross-functional teams that span a variety of technical disciplines.\nOur team continuously seeks innovative approaches to improve chip performance, power efficiency, and area optimization. Success in this role requires creativity, strong analytical and problem-solving skills, and effective written and verbal communication abilities. The candidate enjoys solving challenging technical problems, working collaboratively to develop solutions, and contributing to the success of multiple AMD products.\nAs the organization continues to grow in capability and scale, the candidate will have opportunities to mentor engineers, share technical expertise, and support the development of team capabilities.\nKEY RESPONSIBILITIES:\nCollaborate with Cache and CPU Architects to design, document, and execute optimized high-performance Cache and Routing Fabric designs.\nCollaborate with Physical Design teams to develop RTL optimized for physical implementation and timing closure.\nCollaborate with Design Verification teams to develop architectures and features that are clearly documented and verifiable.\nCollaborate with Design for Test teams to develop RTL that is reliable, testable, and manufacturable.\nWork across global teams to solve complex architectural interactions between IP and SoC designs.\nDevelop improvements to CPU designs by increasing quality, simplifying design complexity through innovation, and strengthening technical collaboration across teams.\nSolve complex design and tool challenges through innovative and practical solutions while contributing to technical excellence across the organization. Create technical presentations for peers and management.\nGuide and mentor other engineers.\nPREFERRED EXPERIENCE:\nPrior experience with Cache architecture development and execution, including Cache Controller and Array RTL implementation.\nPrior experience with CPU Coherency, Coherent NoC, Cache Allocation and Replacement Policy, Quality of Service, Fairness, and Forward Progress architecture and implementation.\nPrior experience collaborating effectively with diverse teams across disciplines.\nPrior experience with Digital RTL Design, Verilog HDL, and scripting.\nACADEMIC CREDENTIALS:\nBachelor’s or master’s degree in computer engineering, Electrical Engineering, or a related technical field.\nThis role is not eligible for visa sponsorship.\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.","description_format":"text","description_chars":8844,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Computer Components","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-10-20T09:28:01Z"}],"visa":[],"liveness":{"score":20,"band":"cold","label":"Long shot","p_open":1,"p_active":0.362,"p_room":0.55,"age_days":29,"expected_fill_days":20,"reasons":["conf:1","stale_co","velocity","win:tail","comp:brand"],"computed_at":"2026-10-23T05:54:15Z"},"pay":null,"html_url":"https://alion.io/job/amd-cpu-microarchitecture-cache-rtl-design-engineer","json_url":"https://alion.io/job/amd-cpu-microarchitecture-cache-rtl-design-engineer.json","meta":{"generated_at":"2026-10-23T13:52:56Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":20763,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-24T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":93},"rest":"https://alion.io/mcp/rest/get_company?id=93"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Famd-cpu-microarchitecture-cache-rtl-design-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Famd-cpu-microarchitecture-cache-rtl-design-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Famd-cpu-microarchitecture-cache-rtl-design-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/amd-cpu-microarchitecture-cache-rtl-design-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Famd-cpu-microarchitecture-cache-rtl-design-engineer"}]}