{"id":2909873,"url":"https://alion.io/job/amd-design-verification-engineer","title":"Design Verification Engineer","company":{"id":93,"name":"AMD","domain":"amd.com","url":"https://alion.io/company/amd","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Jibe","truth_index":{"grade":"B","score":75,"open_postings":163,"ghost_share":0,"stale_share":0.994,"repost_share":0,"time_to_fill_p50_days":28,"computed_at":"2026-10-24T06:02:35Z"}},"role":"Hardware","role_family":"Hardware","seniority":null,"employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Markham, Canada"],"countries":["CA"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":70000,"max_usd":138000,"period":"year","method":"role_country_seniority_unknown","sample_n":146},"experience_years_min":null,"visa_sponsorship":true,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Formal Verification","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Synopsys HAPS","optional":false},{"name":"Synopsys Verdi","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false}],"status":"live","first_seen_at":"2026-10-19T14:37:00Z","employer_posted_date":"2026-10-20","last_verified_at":"2026-10-25T01:47:53Z","board_verified":true,"closed_at":null,"days_open":5,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":5},"description":"ADVANCE YOUR CAREER. ADVANCE THE WORLD.\nAt AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.\nWhether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Join us and, together, we’ll advance your career.\n THE ROLE:\nAMD’s Network Technologies Solutions Group (NTSG) develops advanced networking silicon and software for data center, cloud, and enterprise infrastructure.\nWe are seeking a hands-on Design Verification Engineer to lead verification of complex networking IP, subsystems, and SoCs. You will define verification strategy, develop scalable environments, influence architecture and microarchitecture, and drive functional and performance verification to signoff.\nYou will work on next-generation technologies spanning high-speed Ethernet, PCIe, DMA, packet processing, traffic management, virtualization, and hardware-software interactions.\nTHE PERSON:\nWe are seeking a high-impact Design Verification Engineer with strong technical depth, ownership, and the ability to drive verification closure on complex, high-performance ASIC designs.\nThe ideal candidate brings hands-on verification expertise, excels in debugging intricate architecture/RTL issues, and is comfortable leading verification efforts across IP, subsystem, and SoC levels.\nYou will work in a fast-paced, highly collaborative environment and contribute directly to the success of next-generation AMD networking products.\nKEY RESPONSIBILITIES:\nVerification Architecture & Testbench Development\nDevelop robust UVM-based testbench architectures for IP, subsystem, and SoC-level verification.\nDrive test plan creation, feature mapping, and coverage strategy for complex networking and data-path IP.\nDevelop high-quality SystemVerilog components: stimulus generators, agents, BFMs/transactors, scoreboards, checkers, assertions, and functional coverage models.\nNetworking & Performance Verification\nVerify networking and data-path functions including Ethernet, PCIe, DMA, packet processing, switch fabrics, and traffic management.\nDevelop scenarios covering packet forwarding, buffering, ordering, arbitration, flow control, error handling, and recovery.\nVerify throughput, latency, bandwidth, fairness, QoS, congestion, and other performance requirements using realistic traffic and stress workloads.\nExecution, Debug & Closure\nOwn execution of verification plans, regression triage, and debug of architectural, functional, and performance issues.\nRoot-cause complex failures across RTL, testbench, interfaces (PCIe/DDR/Ethernet), and system interactions.\nOptimize simulations, coverage closure, and verification sign-off methodology.\nTools & Methodology\nUse industry-standard simulation, debug, and analysis tools (VCS, Verdi/DVE, coverage tools, waveform analysis suites).\nContribute to verification methodology improvements, automation, and infrastructure enhancements (Python/Tcl/Make).\nCross-Functional Collaboration\nCollaborate closely with RTL design, architecture, validation, firmware, and emulation/HAPS teams to ensure high-quality deliverables.\nParticipate in design reviews, micro-architecture definition, and bring a verification perspective into early design stages.\nMentor junior engineers and provide technical leadership within the verification team.\nLANGUAGES & TOOLS\nRequired\nExpert-level knowledge of SystemVerilog and UVM\nStrong hands-on experience with SystemVerilog simulators (VCS preferred) and waveform debuggers (Verdi/DVE)\nProven experience in verifying complex IP/subsystems with test plans, coverage, and constrained-random methodologies\nStrong debug skills across architecture, RTL, and testbench layers\nExperience with industry protocols such as PCIe, AXI, Ethernet, DDR, DMA engines, or similar data-path components\nScripting skills in Python, Perl, Shell, Tcl, or equivalent for automation and infrastructure\nPreferred\nPacket-processing pipelines, switch fabrics, schedulers, packet buffers, or traffic managers.\nExperience with performance verification, power-aware verification (UPF), or formal verification\nFamiliarity with FPGA/HAPS-based validation and acceleration flows\nExposure to architectural modeling or C/C++ reference models\nPREFERRED QUALIFICATIONS:\nStrong analytical and problem-solving abilities with a proven track record of debugging complex issues\nAbility to lead verification tasks independently and drive cross-team closure\nExcellent verbal and written communication skills\nComfortable working in a fast-paced, collaborative, multi-site environment\nAbility to mentor and guide junior DV engineers\nACADEMIC CREDENTIALS\nBachelor’s Degree in Electrical/Computer Engineering or related field, Master’s Preferred\nLocation: Markham, ON\nThis role is not eligible for visa sponsorship.\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.\nTHE ROLE:\nAMD’s Network Technologies Solutions Group (NTSG) develops advanced networking silicon and software for data center, cloud, and enterprise infrastructure.\nWe are seeking a hands-on Design Verification Engineer to lead verification of complex networking IP, subsystems, and SoCs. You will define verification strategy, develop scalable environments, influence architecture and microarchitecture, and drive functional and performance verification to signoff.\nYou will work on next-generation technologies spanning high-speed Ethernet, PCIe, DMA, packet processing, traffic management, virtualization, and hardware-software interactions.\nTHE PERSON:\nWe are seeking a high-impact Design Verification Engineer with strong technical depth, ownership, and the ability to drive verification closure on complex, high-performance ASIC designs.\nThe ideal candidate brings hands-on verification expertise, excels in debugging intricate architecture/RTL issues, and is comfortable leading verification efforts across IP, subsystem, and SoC levels.\nYou will work in a fast-paced, highly collaborative environment and contribute directly to the success of next-generation AMD networking products.\nKEY RESPONSIBILITIES:\nVerification Architecture & Testbench Development\nDevelop robust UVM-based testbench architectures for IP, subsystem, and SoC-level verification.\nDrive test plan creation, feature mapping, and coverage strategy for complex networking and data-path IP.\nDevelop high-quality SystemVerilog components: stimulus generators, agents, BFMs/transactors, scoreboards, checkers, assertions, and functional coverage models.\nNetworking & Performance Verification\nVerify networking and data-path functions including Ethernet, PCIe, DMA, packet processing, switch fabrics, and traffic management.\nDevelop scenarios covering packet forwarding, buffering, ordering, arbitration, flow control, error handling, and recovery.\nVerify throughput, latency, bandwidth, fairness, QoS, congestion, and other performance requirements using realistic traffic and stress workloads.\nExecution, Debug & Closure\nOwn execution of verification plans, regression triage, and debug of architectural, functional, and performance issues.\nRoot-cause complex failures across RTL, testbench, interfaces (PCIe/DDR/Ethernet), and system interactions.\nOptimize simulations, coverage closure, and verification sign-off methodology.\nTools & Methodology\nUse industry-standard simulation, debug, and analysis tools (VCS, Verdi/DVE, coverage tools, waveform analysis suites).\nContribute to verification methodology improvements, automation, and infrastructure enhancements (Python/Tcl/Make).\nCross-Functional Collaboration\nCollaborate closely with RTL design, architecture, validation, firmware, and emulation/HAPS teams to ensure high-quality deliverables.\nParticipate in design reviews, micro-architecture definition, and bring a verification perspective into early design stages.\nMentor junior engineers and provide technical leadership within the verification team.\nLANGUAGES & TOOLS\nRequired\nExpert-level knowledge of SystemVerilog and UVM\nStrong hands-on experience with SystemVerilog simulators (VCS preferred) and waveform debuggers (Verdi/DVE)\nProven experience in verifying complex IP/subsystems with test plans, coverage, and constrained-random methodologies\nStrong debug skills across architecture, RTL, and testbench layers\nExperience with industry protocols such as PCIe, AXI, Ethernet, DDR, DMA engines, or similar data-path components\nScripting skills in Python, Perl, Shell, Tcl, or equivalent for automation and infrastructure\nPreferred\nPacket-processing pipelines, switch fabrics, schedulers, packet buffers, or traffic managers.\nExperience with performance verification, power-aware verification (UPF), or formal verification\nFamiliarity with FPGA/HAPS-based validation and acceleration flows\nExposure to architectural modeling or C/C++ reference models\nPREFERRED QUALIFICATIONS:\nStrong analytical and problem-solving abilities with a proven track record of debugging complex issues\nAbility to lead verification tasks independently and drive cross-team closure\nExcellent verbal and written communication skills\nComfortable working in a fast-paced, collaborative, multi-site environment\nAbility to mentor and guide junior DV engineers\nACADEMIC CREDENTIALS\nBachelor’s Degree in Electrical/Computer Engineering or related field, Master’s Preferred\nLocation: Markham, ON\nThis role is not eligible for visa sponsorship.\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. 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