{"id":2909935,"url":"https://alion.io/job/amd-design-verification-technical-lead","title":"Design Verification Technical Lead","company":{"id":93,"name":"AMD","domain":"amd.com","url":"https://alion.io/company/amd","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Jibe","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Ottawa, Canada"],"countries":["CA"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":101000,"max_usd":184000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":16},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Design of Experiments","optional":true}],"status":"live","first_seen_at":"2026-10-16T15:49:00Z","employer_posted_date":"2026-10-20","last_verified_at":"2026-10-21T11:49:04Z","board_verified":true,"closed_at":null,"days_open":4,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":4},"description":"ADVANCE YOUR CAREER. ADVANCE THE WORLD.\nAt AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.\nWhether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Join us and, together, we’ll advance your career.\n THE ROLE:\nThis is a Technical Lead/Manager role for ASIC Hardware and Firmware Co-Verification Engineering role with the Security IP Team (SECIP) in AMD . The primary focus of this role is to Lead and Manage the team responsible for Hardware/Firmware co-verification of various embedded micro-processor subsystems and the associated hardware accelerators in leading edge SOC’s. The preferred candidate will also have proven experience in Firmware based HW verification and the ability to contribute to Firmware development initiatives. These IP subsystems provide high performance functions to the respective SoC, such as security policy management, cryptography, data compression, high throughput DMA, etc.\nTHE PERSON:\nThe ideal candidate has experience leading others in technical and managerial settings. You also have excellent communication, writing, and presentation skills.\nKEY RESPONSIBILITIES:\nLead a high-performance engineering team \nForm a team and nurture talent \nLead team, meet schedule commitments and provide strong support to customers \nCollaborate with multi-functional leaders to drive AMD's success \nResponsible to performance review , career development for team member .\nManaged the team that is responsible for implementing / executing below task\nHardware/Firmware co-verification in UVM System Verilog and C-DPI structured testbench.\nHardware/Firmware co-verification in FPGA hardware prototype platform.\nDevelop and maintain subsystem verification architecture, testbench, test methodology for\nEmbedded CPU and subcomponent IPs with\nAXI/AHB busses and HW accelerators such as\nCryptography, Data Compression, DMA, etc.\nParticipate in subsystem specification, influence IP micro-architecture development (HW and FW co-design and verification aspect), develop and verify abstracted performance model\nCreate abstracted FW and HW performance models\nDevelop critical target code to collect IP performance key parameters\nExplore subsystem architecture performance trade-off for FW and HW optimization\nDrive team to Develop and execute subsystem and block level test plans\nDevelop FW/HW co-verification methodology\nDevelop UVC and System Response models\nDevelop and debug UVM and C-DPI test cases with integrated FW\nImprove verification metrics\nFurther develop subsystem and block level testbenches using UVM randomized test methodology and C-DPI directed test methodology.\nDevelop and maintain subsystem level integration scripts\nDevelop and maintain subsystem testbench build and test run scripts\nDrive to verification metrics closure\nInterface with SoC integration and SoC DV teams\nDefine and develop IP level DV API to support SoC level DV effort\nDevelop and maintain IP build and delivery infrastructure to support SoC level integration of SMU IPs.\nSupport SoC level IP emulation, silicon bring-up and debugging effort\nPREFERRED EXPERIENCE:\nA strong leader with experience working with a distributed team \nStrong mentoring and coaching skills \nProven experience managing and leading engineering teams \nPrior experience in optimizing performance (client, server, system, or embedded) \nStrong system and software engineering background \nStrong communications skills. Able to summarize complex problems for executives as well as drill down to details with architects and engineers \nStrong analytic and problem-solving skills including the ability to analyze current behavior, identify potential areas for improvement and design of experiments \nMust be a self-starter and self-motivated \nPrior experience Managing technical teams \nACADEMIC CREDENTIALS:\nBachelors or Masters degree in computer engineering/Electrical Engineering \nLOCATION: Ottawa, ON\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.\nTHE ROLE:\nThis is a Technical Lead/Manager role for ASIC Hardware and Firmware Co-Verification Engineering role with the Security IP Team (SECIP) in AMD . The primary focus of this role is to Lead and Manage the team responsible for Hardware/Firmware co-verification of various embedded micro-processor subsystems and the associated hardware accelerators in leading edge SOC’s. The preferred candidate will also have proven experience in Firmware based HW verification and the ability to contribute to Firmware development initiatives. These IP subsystems provide high performance functions to the respective SoC, such as security policy management, cryptography, data compression, high throughput DMA, etc.\nTHE PERSON:\nThe ideal candidate has experience leading others in technical and managerial settings. You also have excellent communication, writing, and presentation skills.\nKEY RESPONSIBILITIES:\nLead a high-performance engineering team \nForm a team and nurture talent \nLead team, meet schedule commitments and provide strong support to customers \nCollaborate with multi-functional leaders to drive AMD's success \nResponsible to performance review , career development for team member .\nManaged the team that is responsible for implementing / executing below task\nHardware/Firmware co-verification in UVM System Verilog and C-DPI structured testbench.\nHardware/Firmware co-verification in FPGA hardware prototype platform.\nDevelop and maintain subsystem verification architecture, testbench, test methodology for\nEmbedded CPU and subcomponent IPs with\nAXI/AHB busses and HW accelerators such as\nCryptography, Data Compression, DMA, etc.\nParticipate in subsystem specification, influence IP micro-architecture development (HW and FW co-design and verification aspect), develop and verify abstracted performance model\nCreate abstracted FW and HW performance models\nDevelop critical target code to collect IP performance key parameters\nExplore subsystem architecture performance trade-off for FW and HW optimization\nDrive team to Develop and execute subsystem and block level test plans\nDevelop FW/HW co-verification methodology\nDevelop UVC and System Response models\nDevelop and debug UVM and C-DPI test cases with integrated FW\nImprove verification metrics\nFurther develop subsystem and block level testbenches using UVM randomized test methodology and C-DPI directed test methodology.\nDevelop and maintain subsystem level integration scripts\nDevelop and maintain subsystem testbench build and test run scripts\nDrive to verification metrics closure\nInterface with SoC integration and SoC DV teams\nDefine and develop IP level DV API to support SoC level DV effort\nDevelop and maintain IP build and delivery infrastructure to support SoC level integration of SMU IPs.\nSupport SoC level IP emulation, silicon bring-up and debugging effort\nPREFERRED EXPERIENCE:\nA strong leader with experience working with a distributed team \nStrong mentoring and coaching skills \nProven experience managing and leading engineering teams \nPrior experience in optimizing performance (client, server, system, or embedded) \nStrong system and software engineering background \nStrong communications skills. Able to summarize complex problems for executives as well as drill down to details with architects and engineers \nStrong analytic and problem-solving skills including the ability to analyze current behavior, identify potential areas for improvement and design of experiments \nMust be a self-starter and self-motivated \nPrior experience Managing technical teams \nACADEMIC CREDENTIALS:\nBachelors or Masters degree in computer engineering/Electrical Engineering \nLOCATION: Ottawa, ON\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.","description_format":"text","description_chars":9799,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Computer Components","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-10-20T09:19:33Z"}],"visa":[],"liveness":{"score":90,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.903,"p_room":1,"age_days":4,"expected_fill_days":15,"reasons":["conf:3","velocity","win:early","comp:brand"],"computed_at":"2026-10-21T05:46:15Z"},"pay":null,"html_url":"https://alion.io/job/amd-design-verification-technical-lead","json_url":"https://alion.io/job/amd-design-verification-technical-lead.json","meta":{"generated_at":"2026-10-21T12:27:54Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":17627,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-22T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":93},"rest":"https://alion.io/mcp/rest/get_company?id=93"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Famd-design-verification-technical-lead"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Famd-design-verification-technical-lead"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Famd-design-verification-technical-lead"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/amd-design-verification-technical-lead\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Famd-design-verification-technical-lead"}]}