{"id":3709796,"url":"https://alion.io/job/amd-dft-engineering-director-cpu-cores-design-for-testability","title":"DFT Engineering Director, CPU Cores Design for Testability","company":{"id":93,"name":"AMD","domain":"amd.com","url":"https://alion.io/company/amd","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Jibe","truth_index":{"grade":"A","score":97,"open_postings":17,"ghost_share":0,"stale_share":0.118,"repost_share":0,"time_to_fill_p50_days":49,"computed_at":"2026-11-08T05:47:12Z"}},"role":"Leadership","role_family":"Leadership","seniority":"head","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Austin, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":true,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":true},{"name":"SystemVerilog","optional":true},{"name":"Verilog","optional":true}],"status":"live","first_seen_at":"2026-11-03T20:26:00Z","employer_posted_date":"2026-11-03","last_verified_at":"2026-11-06T09:08:37Z","board_verified":false,"closed_at":null,"days_open":5,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":5},"description":"ADVANCE YOUR CAREER. ADVANCE THE WORLD.\nAt AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.\nWhether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Join us and, together, we’ll advance your career.\nTHE ROLE:\nWe are searching for a senior technical leader to help drive and develop the Design for Testability (DFT) execution and roadmap for future generations of AMD CPUs. This leader will have a high visibility role in future industry-leading CPUs, from concept through production. You will direct the activities of a talented and experienced multi-geography team.\nThis role requires a unique combination of technical expertise, vision, organizational leadership, and operational excellence. You will help shape the future of AMD’s CPU portfolio while developing the next generation of engineering innovators and leaders.\nTHE PERSON:\nYou have strong people leadership and teamwork skills, combined with deep DFT technical expertise and management in a large-scale and complex development environment.\nYou are comfortable operating at executive, leadership, management, and technical levels, influencing organizational strategy, driving critical engineering decisions, mentoring leaders, and representing AMD's technology leadership internally and externally.\nExperience with the x86 architecture is a plus.\nKEY RESPONSIBILITIES\nFunctional management of the DFT organization in a high-performance CPU Cores development team.\nDevelop future DFT features in collaboration with teams and peers across multiple domestic and international sites\nSupport and drive DFT in multiple programs across many generations of the AMD CPU roadmap\nEstablish organizational priorities, operating mechanisms, and execution frameworks that enable predictable delivery of complex programs.\nFoster a culture centered on innovation, inclusion, technical excellence, accountability, and continuous improvement.\nDrive workforce planning, succession planning, leadership development, and organizational growth.\nPREFERRED EXPERIENCE\nExtensive and Senior experience in DFT architecture, design, debug, and verification\nSeveral years of leadership experience in DFT architecture, design, debug, and verification\nKnowledge and expertise in JTAG, ATPG, Scan, MBIST, and LBIST\nFamiliarity with industry standard DFT tools\nFamiliarity and experience with pattern generation, deployment, and debug on ATE \nExperience in concept-to-production development support for DFT activities\nExperience with IP-level debug and verification\nWorking knowledge of Verilog or System Verilog; System C and C++ a plus\nFamiliarity with ICL/PDL\nScripting language experience\nExperience integrating AI into the development environment.\nACADEMIC CREDENTIALS\nBSEE or higher in Electrical or Computer Engineering, MSEE preferred\nLOCATION\nAustin, TX, but can also support: Santa Clara, CA; FT. Collins CO; Boxborough, MA; Fishkill, NY\nThis role is not eligible for visa sponsorship.\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.\nTHE ROLE:\nWe are searching for a senior technical leader to help drive and develop the Design for Testability (DFT) execution and roadmap for future generations of AMD CPUs. This leader will have a high visibility role in future industry-leading CPUs, from concept through production. You will direct the activities of a talented and experienced multi-geography team.\nThis role requires a unique combination of technical expertise, vision, organizational leadership, and operational excellence. You will help shape the future of AMD’s CPU portfolio while developing the next generation of engineering innovators and leaders.\nTHE PERSON:\nYou have strong people leadership and teamwork skills, combined with deep DFT technical expertise and management in a large-scale and complex development environment.\nYou are comfortable operating at executive, leadership, management, and technical levels, influencing organizational strategy, driving critical engineering decisions, mentoring leaders, and representing AMD's technology leadership internally and externally.\nExperience with the x86 architecture is a plus.\nKEY RESPONSIBILITIES\nFunctional management of the DFT organization in a high-performance CPU Cores development team.\nDevelop future DFT features in collaboration with teams and peers across multiple domestic and international sites\nSupport and drive DFT in multiple programs across many generations of the AMD CPU roadmap\nEstablish organizational priorities, operating mechanisms, and execution frameworks that enable predictable delivery of complex programs.\nFoster a culture centered on innovation, inclusion, technical excellence, accountability, and continuous improvement.\nDrive workforce planning, succession planning, leadership development, and organizational growth.\nPREFERRED EXPERIENCE\nExtensive and Senior experience in DFT architecture, design, debug, and verification\nSeveral years of leadership experience in DFT architecture, design, debug, and verification\nKnowledge and expertise in JTAG, ATPG, Scan, MBIST, and LBIST\nFamiliarity with industry standard DFT tools\nFamiliarity and experience with pattern generation, deployment, and debug on ATE \nExperience in concept-to-production development support for DFT activities\nExperience with IP-level debug and verification\nWorking knowledge of Verilog or System Verilog; System C and C++ a plus\nFamiliarity with ICL/PDL\nScripting language experience\nExperience integrating AI into the development environment.\nACADEMIC CREDENTIALS\nBSEE or higher in Electrical or Computer Engineering, MSEE preferred\nLOCATION\nAustin, TX, but can also support: Santa Clara, CA; FT. Collins CO; Boxborough, MA; Fishkill, NY\nThis role is not eligible for visa sponsorship.\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.","description_format":"text","description_chars":7912,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Computer Components","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-11-03T22:27:22Z"}],"visa":[],"liveness":{"score":90,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.903,"p_room":1,"age_days":4,"expected_fill_days":49,"reasons":["conf:44","velocity","win:early","comp:brand"],"computed_at":"2026-11-08T05:47:12Z"},"pay":null,"html_url":"https://alion.io/job/amd-dft-engineering-director-cpu-cores-design-for-testability","json_url":"https://alion.io/job/amd-dft-engineering-director-cpu-cores-design-for-testability.json","meta":{"generated_at":"2026-11-09T03:12:01Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":1140,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-10T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.1,"usd":0.01,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":93},"rest":"https://alion.io/mcp/rest/get_company?id=93"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Famd-dft-engineering-director-cpu-cores-design-for-testability"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":2,"usd":0.2},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Famd-dft-engineering-director-cpu-cores-design-for-testability"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.1,"usd":0.01},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Famd-dft-engineering-director-cpu-cores-design-for-testability"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/amd-dft-engineering-director-cpu-cores-design-for-testability\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Famd-dft-engineering-director-cpu-cores-design-for-testability"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":3709796}},{"tool":"search_jobs","arguments":{"company":"amd.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":3709796},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. 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