{"id":2910550,"url":"https://alion.io/job/amd-dftdfx-architecture-rtl-lead","title":"DFT/DFx Architecture & RTL Lead","company":{"id":93,"name":"AMD","domain":"amd.com","url":"https://alion.io/company/amd","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Jibe","truth_index":{"grade":"A","score":97,"open_postings":17,"ghost_share":0,"stale_share":0.118,"repost_share":0,"time_to_fill_p50_days":49,"computed_at":"2026-11-08T05:47:12Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Santa Clara, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":190000,"max_usd":353000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":656},"experience_years_min":null,"visa_sponsorship":true,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Synopsys SpyGlass","optional":false},{"name":"Synopsys VCS","optional":false},{"name":"Synopsys Verdi","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Tessent","optional":false},{"name":"Verilog","optional":false}],"status":"closed","first_seen_at":"2026-10-05T19:47:00Z","employer_posted_date":"2026-11-04","last_verified_at":"2026-11-05T09:32:48Z","board_verified":false,"closed_at":"2026-11-05T09:32:48Z","days_open":30,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":30},"description":"ADVANCE YOUR CAREER. ADVANCE THE WORLD.\nAt AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.\nWhether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Join us and, together, we’ll advance your career.\nTHE ROLE:\nThe Circuit Technology team is looking for an experienced DFT/DFx Methodology, Architecture, and RTL Execution Lead to support high-speed SerDes PHYs, next-generation Memory PHYs, and die-to-die interconnect IPs.\nIn this role, you will own and lead DFT/DFx architecture definition, RTL implementation, methodology development, scan integration support, test constraints, ATPG support, and post-silicon debug for advanced PHY and connectivity IP designs. You will collaborate closely with design, verification, physical design, CAD, product engineering, and test engineering teams to deliver robust, high-coverage, production-ready IP.\nBe part of a collaborative team delivering advanced IP used across SoCs.\nTHE PERSON:\nThe successful candidate brings analytical and problem-solving skills, attention to technical quality, and the ability to lead complex technical work with appropriate autonomy and cross-functional collaboration. The candidate should be able to contribute directly to technical implementation while providing technical leadership across architecture, methodology, RTL implementation, verification, and silicon debug.\nKEY RESPONSIBILITIES:\nDefine and lead PHY-specific DFT/DFx architecture and methodology for high-speed SerDes, Memory PHY, and die-to-die interconnect IPs.\nImplement DFT/DFx features in RTL using Verilog/SystemVerilog.\nDevelop and support DFT micro-architecture, including scan architecture, test modes, clocking, reset, isolation, bypass, and observability features.\nSupport JTAG/IJTAG, ICL/PDL, scan compression, at-speed scan, and hierarchical DFT implementation.\nSupport Siemens Tessent-based or equivalent industry-standard DFT flows for ATPG, pattern generation, pattern validation, and debug.\nSupport scan stitching, scan-readiness checks, test coverage analysis, and DFT rule/debug closure.\nDevelop and maintain DFT timing constraints, test-mode constraints, and integration guidelines compatible with front-end and physical design flows.\nPerform gate-level simulation and debug using tools such as Synopsys VCS and Verdi or comparable tools.\nDrive SpyGlass or equivalent lint/DFT-readiness analysis to identify scan, controllability, observability, and test coverage gaps.\nPlan, implement, and verify MBIST-related features for embedded memories.\nSupport ATPG pattern generation, simulation, debug, and delivery to test engineering.\nPartner with Test Engineering and Product Engineering on silicon bring-up, tester pattern debug, diagnosis, and yield-learning activities.\nDevelop efficient and reusable DFx flows, scripts, checkers, and methodologies for IP-level and SoC-level integration.\nPREFERRED EXPERIENCE:\nRelevant industry experience in DFT, DFx, RTL design, semiconductor IP development, or SoC test methodology. Level will be determined based on demonstrated technical scope, relevant experience, and role-related interview criteria.\nUnderstanding of DFT architecture and micro-architectures, including scan, compression, test clocks, test resets, lock-up latches, clock gates, scan anchors, and test access mechanisms.\nHands-on experience with Siemens Tessent DFT flows, such as Tessent Shell, Tessent Scan, Tessent ATPG, Tessent TestKompress, Tessent MemoryBIST, IJTAG, ICL/PDL, and/or Streaming Scan Network/SSN, or experience with comparable industry-standard DFT tools and methodologies.\nExperience developing or supporting hierarchical DFT flows for complex SoCs or reusable IPs.\nHands-on RTL coding experience in Verilog and/or SystemVerilog.\nExperience with industry-standard ATPG, scan insertion, and DFT implementation tools.\nFamiliarity with JTAG, IJTAG, ICL/PDL, scan compression, at-speed scan, and hierarchical DFT concepts.\nExperience with gate-level simulation, debug, and waveform analysis using tools such as Synopsys VCS and Verdi or comparable technologies.\nExperience analyzing DFT readiness, lint, controllability, observability, and test coverage issues.\nUnderstanding of MBIST planning, implementation, verification, and debug.\nUnderstanding of low-power design concepts such as power gating, multi-voltage domains, multi-Vt usage, isolation, retention, and voltage scaling.\nUnderstanding of high-performance and low-power digital design fundamentals.\nKnowledge of common fault models, including stuck-at, transition, path delay, gate-exhaustive, IDDQ, and cell-aware fault models.\nDemonstrated ability to investigate and resolve issues across RTL, gate-level netlists, constraints, patterns, and silicon behavior.\nAbility to communicate technical information effectively and collaborate across design, verification, CAD, physical design, and test engineering teams.\nCandidates are encouraged to apply even if their experience does not include every tool or technology listed above. Experience with comparable tools, methodologies, and technically relevant environments may also be considered.\nACADEMIC CREDENTIALS:\nBS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent relevant technical education and industry experience where appropriate.\nThis role is not eligible for visa sponsorship.\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.\nTHE ROLE:\nThe Circuit Technology team is looking for an experienced DFT/DFx Methodology, Architecture, and RTL Execution Lead to support high-speed SerDes PHYs, next-generation Memory PHYs, and die-to-die interconnect IPs.\nIn this role, you will own and lead DFT/DFx architecture definition, RTL implementation, methodology development, scan integration support, test constraints, ATPG support, and post-silicon debug for advanced PHY and connectivity IP designs. You will collaborate closely with design, verification, physical design, CAD, product engineering, and test engineering teams to deliver robust, high-coverage, production-ready IP.\nBe part of a collaborative team delivering advanced IP used across SoCs.\nTHE PERSON:\nThe successful candidate brings analytical and problem-solving skills, attention to technical quality, and the ability to lead complex technical work with appropriate autonomy and cross-functional collaboration. The candidate should be able to contribute directly to technical implementation while providing technical leadership across architecture, methodology, RTL implementation, verification, and silicon debug.\nKEY RESPONSIBILITIES:\nDefine and lead PHY-specific DFT/DFx architecture and methodology for high-speed SerDes, Memory PHY, and die-to-die interconnect IPs.\nImplement DFT/DFx features in RTL using Verilog/SystemVerilog.\nDevelop and support DFT micro-architecture, including scan architecture, test modes, clocking, reset, isolation, bypass, and observability features.\nSupport JTAG/IJTAG, ICL/PDL, scan compression, at-speed scan, and hierarchical DFT implementation.\nSupport Siemens Tessent-based or equivalent industry-standard DFT flows for ATPG, pattern generation, pattern validation, and debug.\nSupport scan stitching, scan-readiness checks, test coverage analysis, and DFT rule/debug closure.\nDevelop and maintain DFT timing constraints, test-mode constraints, and integration guidelines compatible with front-end and physical design flows.\nPerform gate-level simulation and debug using tools such as Synopsys VCS and Verdi or comparable tools.\nDrive SpyGlass or equivalent lint/DFT-readiness analysis to identify scan, controllability, observability, and test coverage gaps.\nPlan, implement, and verify MBIST-related features for embedded memories.\nSupport ATPG pattern generation, simulation, debug, and delivery to test engineering.\nPartner with Test Engineering and Product Engineering on silicon bring-up, tester pattern debug, diagnosis, and yield-learning activities.\nDevelop efficient and reusable DFx flows, scripts, checkers, and methodologies for IP-level and SoC-level integration.\nPREFERRED EXPERIENCE:\nRelevant industry experience in DFT, DFx, RTL design, semiconductor IP development, or SoC test methodology. Level will be determined based on demonstrated technical scope, relevant experience, and role-related interview criteria.\nUnderstanding of DFT architecture and micro-architectures, including scan, compression, test clocks, test resets, lock-up latches, clock gates, scan anchors, and test access mechanisms.\nHands-on experience with Siemens Tessent DFT flows, such as Tessent Shell, Tessent Scan, Tessent ATPG, Tessent TestKompress, Tessent MemoryBIST, IJTAG, ICL/PDL, and/or Streaming Scan Network/SSN, or experience with comparable industry-standard DFT tools and methodologies.\nExperience developing or supporting hierarchical DFT flows for complex SoCs or reusable IPs.\nHands-on RTL coding experience in Verilog and/or SystemVerilog.\nExperience with industry-standard ATPG, scan insertion, and DFT implementation tools.\nFamiliarity with JTAG, IJTAG, ICL/PDL, scan compression, at-speed scan, and hierarchical DFT concepts.\nExperience with gate-level simulation, debug, and waveform analysis using tools such as Synopsys VCS and Verdi or comparable technologies.\nExperience analyzing DFT readiness, lint, controllability, observability, and test coverage issues.\nUnderstanding of MBIST planning, implementation, verification, and debug.\nUnderstanding of low-power design concepts such as power gating, multi-voltage domains, multi-Vt usage, isolation, retention, and voltage scaling.\nUnderstanding of high-performance and low-power digital design fundamentals.\nKnowledge of common fault models, including stuck-at, transition, path delay, gate-exhaustive, IDDQ, and cell-aware fault models.\nDemonstrated ability to investigate and resolve issues across RTL, gate-level netlists, constraints, patterns, and silicon behavior.\nAbility to communicate technical information effectively and collaborate across design, verification, CAD, physical design, and test engineering teams.\nCandidates are encouraged to apply even if their experience does not include every tool or technology listed above. Experience with comparable tools, methodologies, and technically relevant environments may also be considered.\nACADEMIC CREDENTIALS:\nBS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent relevant technical education and industry experience where appropriate.\nThis role is not eligible for visa sponsorship.\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. 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