{"id":2910829,"url":"https://alion.io/job/amd-lead-design-verification-engineer-memory-controller","title":"Lead Design Verification Engineer-Memory Controller","company":{"id":93,"name":"AMD","domain":"amd.com","url":"https://alion.io/company/amd","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Jibe","truth_index":{"grade":"B","score":78,"open_postings":158,"ghost_share":0,"stale_share":0.873,"repost_share":0,"time_to_fill_p50_days":34,"computed_at":"2026-11-01T06:10:25Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["San Jose, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":187000,"max_usd":347000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":656},"experience_years_min":6,"visa_sponsorship":true,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Formal Verification","optional":false},{"name":"UVM","optional":false},{"name":"Cadence JasperGold","optional":true},{"name":"Cadence Xcelium","optional":true},{"name":"Synopsys VC Formal","optional":true},{"name":"Synopsys VCS","optional":true},{"name":"SystemVerilog","optional":true}],"status":"live","first_seen_at":"2026-09-22T18:19:00Z","employer_posted_date":"2026-10-31","last_verified_at":"2026-11-01T14:06:37Z","board_verified":true,"closed_at":null,"days_open":39,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":39},"description":"ADVANCE YOUR CAREER. ADVANCE THE WORLD.\nAt AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.\nWhether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Join us and, together, we’ll advance your career.\nTHE ROLE:\nAdaptive and Embedded Computing Group (AECG) seeks a Senior Staff Silicon Design Verification Engineer to provide technical leadership and expertise in the verification of cutting-edge DRAM Memory Controller IPs (DDR5, LPDDR6, HBM4), high-speed Crypto, and Network-on-Chip (NoC). You will be responsible for architecting, developing, and utilizing simulation and/or formal-based verification environments at both block and SoC-level to achieve first-pass silicon success.\nTHE PERSON:\nThe ideal candidate has a proven track record in driving strategies and successfully executing verification strategies for Pre-Silicon Design IP and/or SOC designs. They should be strong team players with excellent communication and leadership skills, capable of positively and strategically influencing design teams to improve overall product quality.\nKey Responsibilities:\nLead the verification of high-speed Crypto, Network-on-Chip (NoC), cutting-edge DRAM Memory controller (DDR5, LPDDR6, HBM4) designs, ensuring the highest standards of quality and performance.\nArchitect, develop, and use simulation and/or formal-based verification environments at IP and SoC-level.\nLead and manage verification teams, including planning, execution, tracking, verification closure, and delivery to programs.\nDevelop and execute comprehensive verification plans, including testbenches and test cases.\nCollaborate with design, architecture, and software teams to define and implement verification strategies.\nUtilize advanced verification methodologies, including UVM, formal verification, and assertion-based verification.\nMentor and guide junior engineers, fostering a collaborative and innovative team environment.\nPREFERRED EXPERIENCE:\nRequire hands on experience with verification of state-of-the-art memory controllers such as DDR, LPDDR, and HBM. Requires strong understanding of current memory controller protocols and calibration (DDR3/4/5, LPDDR4/5/6, HBM2/3/4), board skew and jitter modeling.\nRequire proven track record in technical leadership of teams with 5+ engineers. This includes planning, execution, tracking, verification closure, and delivery to programs.\nRequire experience with development of UVM and System Verilog test benches and usage of simulation tools/debug environments such as Synopsys VCS or Cadence Xcelium.\nRequire strong understanding of state of the art of verification techniques, including assertion and metric-driven verification. Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high-performance IP and/or VLSI designs is a plus. \nRequire familiarity with verification management tools as well as an understanding of database management particularly as it pertains to regression management.\nExperience with formal property checking tools such as VC Formal (Synopsys), JasperGold (Cadence), and Questa Formal (Mentor) is a plus.\nExperience with gate-level simulation, power-aware verification is a plus.\nExperience with silicon debug at the tester and board level, is a plus.\nACADEMIC CREDENTIALS:\nRequire BS w/ 8+ yrs or MS w/ 6+ yrs or PhD w/ 3+ yrs in Electrical Engineering, Computer Engineering, or Computer Science.\nThis is a 5 Day per week onsite role in San Jose.\nThis role is not eligible for visa sponsorship.\n#LI-RL1\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.\nTHE ROLE:\nAdaptive and Embedded Computing Group (AECG) seeks a Senior Staff Silicon Design Verification Engineer to provide technical leadership and expertise in the verification of cutting-edge DRAM Memory Controller IPs (DDR5, LPDDR6, HBM4), high-speed Crypto, and Network-on-Chip (NoC). You will be responsible for architecting, developing, and utilizing simulation and/or formal-based verification environments at both block and SoC-level to achieve first-pass silicon success.\nTHE PERSON:\nThe ideal candidate has a proven track record in driving strategies and successfully executing verification strategies for Pre-Silicon Design IP and/or SOC designs. They should be strong team players with excellent communication and leadership skills, capable of positively and strategically influencing design teams to improve overall product quality.\nKey Responsibilities:\nLead the verification of high-speed Crypto, Network-on-Chip (NoC), cutting-edge DRAM Memory controller (DDR5, LPDDR6, HBM4) designs, ensuring the highest standards of quality and performance.\nArchitect, develop, and use simulation and/or formal-based verification environments at IP and SoC-level.\nLead and manage verification teams, including planning, execution, tracking, verification closure, and delivery to programs.\nDevelop and execute comprehensive verification plans, including testbenches and test cases.\nCollaborate with design, architecture, and software teams to define and implement verification strategies.\nUtilize advanced verification methodologies, including UVM, formal verification, and assertion-based verification.\nMentor and guide junior engineers, fostering a collaborative and innovative team environment.\nPREFERRED EXPERIENCE:\nRequire hands on experience with verification of state-of-the-art memory controllers such as DDR, LPDDR, and HBM. Requires strong understanding of current memory controller protocols and calibration (DDR3/4/5, LPDDR4/5/6, HBM2/3/4), board skew and jitter modeling.\nRequire proven track record in technical leadership of teams with 5+ engineers. This includes planning, execution, tracking, verification closure, and delivery to programs.\nRequire experience with development of UVM and System Verilog test benches and usage of simulation tools/debug environments such as Synopsys VCS or Cadence Xcelium.\nRequire strong understanding of state of the art of verification techniques, including assertion and metric-driven verification. Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high-performance IP and/or VLSI designs is a plus. \nRequire familiarity with verification management tools as well as an understanding of database management particularly as it pertains to regression management.\nExperience with formal property checking tools such as VC Formal (Synopsys), JasperGold (Cadence), and Questa Formal (Mentor) is a plus.\nExperience with gate-level simulation, power-aware verification is a plus.\nExperience with silicon debug at the tester and board level, is a plus.\nACADEMIC CREDENTIALS:\nRequire BS w/ 8+ yrs or MS w/ 6+ yrs or PhD w/ 3+ yrs in Electrical Engineering, Computer Engineering, or Computer Science.\nThis is a 5 Day per week onsite role in San Jose.\nThis role is not eligible for visa sponsorship.\n#LI-RL1\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.","description_format":"text","description_chars":9088,"description_truncated":false,"requirements":{"experience_years_min":6,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"phd","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Blockchain & Crypto","Processors, MCUs & AI Chips","Computer Components","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-10-20T09:28:01Z"},{"event":"close","at":"2026-10-31T13:38:47Z"},{"event":"reopen","at":"2026-10-31T17:13:40Z"}],"visa":[],"liveness":{"score":32,"band":"fade","label":"Fading","p_open":1,"p_active":0.579,"p_room":0.55,"age_days":39,"expected_fill_days":34,"reasons":["conf:2","stale_co","velocity","win:tail","comp:brand"],"computed_at":"2026-11-01T06:10:25Z"},"pay":null,"html_url":"https://alion.io/job/amd-lead-design-verification-engineer-memory-controller","json_url":"https://alion.io/job/amd-lead-design-verification-engineer-memory-controller.json","meta":{"generated_at":"2026-11-01T18:00:02Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":27540,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-02T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":93},"rest":"https://alion.io/mcp/rest/get_company?id=93"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Famd-lead-design-verification-engineer-memory-controller"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Famd-lead-design-verification-engineer-memory-controller"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Famd-lead-design-verification-engineer-memory-controller"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/amd-lead-design-verification-engineer-memory-controller\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Famd-lead-design-verification-engineer-memory-controller"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":2910829}},{"tool":"search_jobs","arguments":{"company":"amd.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":2910829},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. 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