{"id":2912235,"url":"https://alion.io/job/amd-lead-diagnostics-software-engineer-ate-integration-3","title":"Lead Diagnostics Software Engineer, ATE Integration","company":{"id":93,"name":"AMD","domain":"amd.com","url":"https://alion.io/company/amd","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Jibe","truth_index":null},"role":"Backend","role_family":"Backend","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Austin, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":149000,"max_usd":298000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":1150},"experience_years_min":null,"visa_sponsorship":true,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Advantest / Teradyne ATE","optional":true},{"name":"C++","optional":true},{"name":"CI/CD","optional":true},{"name":"GitHub","optional":true},{"name":"LLM","optional":true},{"name":"Python","optional":true}],"status":"live","first_seen_at":"2026-05-27T20:43:00Z","employer_posted_date":"2026-10-20","last_verified_at":"2026-10-21T21:15:51Z","board_verified":true,"closed_at":null,"days_open":147,"trust":{"level":"stale","repost_count":0,"flags":["stale"],"days_open":146},"description":"WHAT YOU DO AT AMD CHANGES EVERYTHING\nAt AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gamingand embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuityand a shared passion to create something extraordinary. When you join AMD, you’lldiscover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.Together, we advance your career.\nTHE ROLE:\nAs the semiconductor industry pivots toward complex chiplet architectures and hyper-dense data center accelerators, the economics of quality necessitate shifting validation earlier in the production lifecycle. We are seeking a visionary Lead/Principal Diagnostics Engineer to drive our shift from proven post-silicon software validation frameworks and System-Level Tests (SLT) directly into Automated Test Equipment (ATE) and Wafer Sort environments.\nTHE PERSON:\nIn this role, you will bridge the gap between platform-level software execution and traditional hardware-driven manufacturing test patterns. You will design the architecture, tooling, and translation methodologies required to pack, convert, and stream complex software-driven GFX and compute test cases into robust, production-grade ATE patterns. This is a high-impact role requiring deep knowledge of system software/hardware interactions, graphics IP mechanics, and high-volume structural/functional manufacturing test domains.\nKEY RESPONSIBILTIIES\nStrategic Technical Leadership: Define the technical roadmap, architecture, and deployment strategy for migrating post-silicon SLT and functional GFX IP feature diagnostics onto wafer sort and ATE hardware configurations.\n Pattern Generation & Conversion: Architect and develop software utilities/pipelines to convert functional diagnostic sequences, register configurations, and compute workloads into cycle-accurate vector formats (e.g., STIL, WGL, or proprietary tester formats) compatible with high-end ATE testers.\n Cross-Domain Collaboration: Serve as the primary technical liaison between the GFX/Compute Diagnostics team, Product/Test Engineering, and Design-for-Test (DFT) teams\n Platform Integration & Emulation: Analyze existing platform-level hardware/software dependencies (such as sideband management interfaces, firmware, and power management behaviors) to build deterministic, tester-friendly models that emulate host behaviors on ATE hardware.\n Test Coverage & Cost Optimization: Optimize tester execution times (test cost reduction) while maximizing structural and functional test coverage for data center GPU IPs, focusing on massively parallel compute pipelines, high-bandwidth memory (HBM) controllers, and matrix math engines.\nPREFERRED EXPERIENCE:\nExperience: Proven industry experience in silicon engineering spanning post-silicon validation, product engineering, diagnostics development, or structural/functional test generation.\nPlatform HW/SW Proficiency: Strong programming background in C/C++ and Python, with a concrete understanding of bare-metal or driver-level programming, registers, firmware interactions, and system memory maps.\n ATE Knoweldge: Proven hands-on experience with production-grade Automated Test Equipment platforms (e.g., V93000, UltraFLEX) and structural/functional testing at the wafer sort or final test level.\n Pattern Flow Knowledge: Expert understanding of structural pattern generation, vector timing, clock domains, and diagnostic patterns (such as functional vectors, BIST/MBIST, or scan compression output).\nFamiliarity with high-volume manufacturing challenges unique to data center architectures, including high-power profiles, HBM integration, and multi-die chiplet interconnect protocols (e.g., UCIe, proprietary fabrics).\nDeep understanding of GFX and compute architectures, with proven ability to design and implement diagnostic and test cases that maximize coverage and proactively identify silicon issues early\nUnderstanding of AI/ML principles and some experience in applying LLM & ML models in applications\nExperience with working in DevOps environment like GitHub, CI/CD pipelines \nExcellent problem-solving abilities with a keen eye for detail are highly valued\nACADEMIC CREDENTIALS:\nEducation: Bachelor’s, Master’s, or Ph.D. in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.\nLOCATION:\nAustin,TX\nThis role is not eligible for visa sponsorship.\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.\nTHE ROLE:\nAs the semiconductor industry pivots toward complex chiplet architectures and hyper-dense data center accelerators, the economics of quality necessitate shifting validation earlier in the production lifecycle. We are seeking a visionary Lead/Principal Diagnostics Engineer to drive our shift from proven post-silicon software validation frameworks and System-Level Tests (SLT) directly into Automated Test Equipment (ATE) and Wafer Sort environments.\nTHE PERSON:\nIn this role, you will bridge the gap between platform-level software execution and traditional hardware-driven manufacturing test patterns. You will design the architecture, tooling, and translation methodologies required to pack, convert, and stream complex software-driven GFX and compute test cases into robust, production-grade ATE patterns. This is a high-impact role requiring deep knowledge of system software/hardware interactions, graphics IP mechanics, and high-volume structural/functional manufacturing test domains.\nKEY RESPONSIBILTIIES\nStrategic Technical Leadership: Define the technical roadmap, architecture, and deployment strategy for migrating post-silicon SLT and functional GFX IP feature diagnostics onto wafer sort and ATE hardware configurations.\n Pattern Generation & Conversion: Architect and develop software utilities/pipelines to convert functional diagnostic sequences, register configurations, and compute workloads into cycle-accurate vector formats (e.g., STIL, WGL, or proprietary tester formats) compatible with high-end ATE testers.\n Cross-Domain Collaboration: Serve as the primary technical liaison between the GFX/Compute Diagnostics team, Product/Test Engineering, and Design-for-Test (DFT) teams\n Platform Integration & Emulation: Analyze existing platform-level hardware/software dependencies (such as sideband management interfaces, firmware, and power management behaviors) to build deterministic, tester-friendly models that emulate host behaviors on ATE hardware.\n Test Coverage & Cost Optimization: Optimize tester execution times (test cost reduction) while maximizing structural and functional test coverage for data center GPU IPs, focusing on massively parallel compute pipelines, high-bandwidth memory (HBM) controllers, and matrix math engines.\nPREFERRED EXPERIENCE:\nExperience: Proven industry experience in silicon engineering spanning post-silicon validation, product engineering, diagnostics development, or structural/functional test generation.\nPlatform HW/SW Proficiency: Strong programming background in C/C++ and Python, with a concrete understanding of bare-metal or driver-level programming, registers, firmware interactions, and system memory maps.\n ATE Knoweldge: Proven hands-on experience with production-grade Automated Test Equipment platforms (e.g., V93000, UltraFLEX) and structural/functional testing at the wafer sort or final test level.\n Pattern Flow Knowledge: Expert understanding of structural pattern generation, vector timing, clock domains, and diagnostic patterns (such as functional vectors, BIST/MBIST, or scan compression output).\nFamiliarity with high-volume manufacturing challenges unique to data center architectures, including high-power profiles, HBM integration, and multi-die chiplet interconnect protocols (e.g., UCIe, proprietary fabrics).\nDeep understanding of GFX and compute architectures, with proven ability to design and implement diagnostic and test cases that maximize coverage and proactively identify silicon issues early\nUnderstanding of AI/ML principles and some experience in applying LLM & ML models in applications\nExperience with working in DevOps environment like GitHub, CI/CD pipelines \nExcellent problem-solving abilities with a keen eye for detail are highly valued\nACADEMIC CREDENTIALS:\nEducation: Bachelor’s, Master’s, or Ph.D. in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.\nLOCATION:\nAustin,TX\nThis role is not eligible for visa sponsorship.\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. 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