{"id":3323475,"url":"https://alion.io/job/amd-lead-fpga-timing-characterization-silicon-design-engineer","title":"Lead FPGA Timing & Characterization Silicon Design Engineer","company":{"id":93,"name":"AMD","domain":"amd.com","url":"https://alion.io/company/amd","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Jibe","truth_index":{"grade":"B","score":75,"open_postings":164,"ghost_share":0,"stale_share":0.994,"repost_share":0,"time_to_fill_p50_days":29,"computed_at":"2026-10-27T05:46:45Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hyderabad, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":26000,"max_usd":59000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":796},"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Xilinx Vivado","optional":false}],"status":"live","first_seen_at":"2026-10-27T06:03:00Z","employer_posted_date":"2026-10-27","last_verified_at":"2026-10-27T22:52:13Z","board_verified":true,"closed_at":null,"days_open":0,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":0},"description":"ADVANCE YOUR CAREER. ADVANCE THE WORLD.\nAt AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.\nWhether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Join us and, together, we’ll advance your career.\nLead FPGA Timing & Characterization Silicon Design Engineer\n\nWe are seeking a highly motivated and experienced Senior Member of Technical Staff (SMTS) to lead the development, validation, silicon correlation, and release of FPGA timing models. The successful candidate will drive timing characterization methodologies, improve timing model quality and accuracy, collaborate across architecture, silicon design, STA, software, and validation teams, and ensure timely delivery of production-quality timing models that enable industry-leading FPGA implementation and timing analysis tools.\nRoles and Responsibilities\nEstablish comprehensive validation frameworks for FPGA timing library quality assessment.\n\nDrive root-cause analysis for timing discrepancies and model inaccuracies.\n\nDevelop and maintain regression suites, DRC checks, and release signoff criteria.\nDrive characterization of FPGA resources\n\nDevelop automation flows to improve FPGA timing quality\n\nOwn planning and execution of Timing Library releases aligned with software release schedules.\n\nPerform QoR analysis on Vivado software and compare timing results across releases, speed grades, and device generations.\n\nCoordinate release readiness reviews and manage risk mitigation plans.\n\nProvide technical status updates to engineering leadership and product stakeholders.\n\nRequired Qualifications\nMTech or MS in Electronics Engineering.\n\n10+ years of experience in FPGA design development & implementation, timing analysis, Silicon characterization\n\nStrong understanding of:\nFPGA architecture and timing closure\n\nStatic Timing Analysis (STA), PVT variation and timing margins, OCV/POCV methodologies\n\nExperience with silicon characterization and model generation flows.\n\nProficiency in scripting and automation using Python, Perl, Tcl, or similar languages.\nStrong debugging and root-cause analysis skills.\n\nFamiliarity with large-scale flow automation and data analytics.\n\nExperience with Vivado or Quartus FPGA tools\n\nKnowledge of silicon correlation and statistical timing techniques.\nExperience leading cross-functional technical initiatives.\n\nExpectations:\nServe as the technical authority for FPGA timing library methodologies and releases.\n\nDrive improvements in prediction accuracy, release quality, and characterization productivity.\nInfluence roadmaps, timing methodologies, and next-generation FPGA timing modeling strategies.\nMentor engineers and establish engineering best practices across the organization.\nLead technically challenging projects with significant product and customer impact.\nSuccess Metrics\nOn-time delivery of timing library releases.\n\nSilicon correlation accuracy improvement.\nReduction in customer timing escapes.\nImproved QoR consistency across releases.\nIncreased automation and productivity of characterization flows.\nSuccessful execution of strategic timing-modeling initiatives.\n\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.\nLead FPGA Timing & Characterization Silicon Design Engineer\n\nWe are seeking a highly motivated and experienced Senior Member of Technical Staff (SMTS) to lead the development, validation, silicon correlation, and release of FPGA timing models. The successful candidate will drive timing characterization methodologies, improve timing model quality and accuracy, collaborate across architecture, silicon design, STA, software, and validation teams, and ensure timely delivery of production-quality timing models that enable industry-leading FPGA implementation and timing analysis tools.\nRoles and Responsibilities\nEstablish comprehensive validation frameworks for FPGA timing library quality assessment.\n\nDrive root-cause analysis for timing discrepancies and model inaccuracies.\n\nDevelop and maintain regression suites, DRC checks, and release signoff criteria.\nDrive characterization of FPGA resources\n\nDevelop automation flows to improve FPGA timing quality\n\nOwn planning and execution of Timing Library releases aligned with software release schedules.\n\nPerform QoR analysis on Vivado software and compare timing results across releases, speed grades, and device generations.\n\nCoordinate release readiness reviews and manage risk mitigation plans.\n\nProvide technical status updates to engineering leadership and product stakeholders.\n\nRequired Qualifications\nMTech or MS in Electronics Engineering.\n\n10+ years of experience in FPGA design development & implementation, timing analysis, Silicon characterization\n\nStrong understanding of:\nFPGA architecture and timing closure\n\nStatic Timing Analysis (STA), PVT variation and timing margins, OCV/POCV methodologies\n\nExperience with silicon characterization and model generation flows.\n\nProficiency in scripting and automation using Python, Perl, Tcl, or similar languages.\nStrong debugging and root-cause analysis skills.\n\nFamiliarity with large-scale flow automation and data analytics.\n\nExperience with Vivado or Quartus FPGA tools\n\nKnowledge of silicon correlation and statistical timing techniques.\nExperience leading cross-functional technical initiatives.\n\nExpectations:\nServe as the technical authority for FPGA timing library methodologies and releases.\n\nDrive improvements in prediction accuracy, release quality, and characterization productivity.\nInfluence roadmaps, timing methodologies, and next-generation FPGA timing modeling strategies.\nMentor engineers and establish engineering best practices across the organization.\nLead technically challenging projects with significant product and customer impact.\nSuccess Metrics\nOn-time delivery of timing library releases.\n\nSilicon correlation accuracy improvement.\nReduction in customer timing escapes.\nImproved QoR consistency across releases.\nIncreased automation and productivity of characterization flows.\nSuccessful execution of strategic timing-modeling initiatives.\n\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.","description_format":"text","description_chars":8228,"description_truncated":false,"requirements":{"experience_years_min":10,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"master","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Computer Components","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-10-27T08:57:26Z"}],"visa":[],"liveness":{"score":86,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.86,"p_room":1,"age_days":0,"expected_fill_days":29,"reasons":["conf:1","win:early","comp:brand"],"computed_at":"2026-10-28T00:21:39Z"},"pay":null,"html_url":"https://alion.io/job/amd-lead-fpga-timing-characterization-silicon-design-engineer","json_url":"https://alion.io/job/amd-lead-fpga-timing-characterization-silicon-design-engineer.json","meta":{"generated_at":"2026-10-28T00:21:39Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":323,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-29T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":93},"rest":"https://alion.io/mcp/rest/get_company?id=93"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Famd-lead-fpga-timing-characterization-silicon-design-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Famd-lead-fpga-timing-characterization-silicon-design-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Famd-lead-fpga-timing-characterization-silicon-design-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/amd-lead-fpga-timing-characterization-silicon-design-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Famd-lead-fpga-timing-characterization-silicon-design-engineer"}]}