{"id":2911458,"url":"https://alion.io/job/amd-lead-ip-verification-engineer-2","title":"Lead IP Verification Engineer","company":{"id":93,"name":"AMD","domain":"amd.com","url":"https://alion.io/company/amd","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Jibe","truth_index":{"grade":"B","score":75,"open_postings":162,"ghost_share":0,"stale_share":0.994,"repost_share":0,"time_to_fill_p50_days":29,"computed_at":"2026-10-25T05:49:26Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Markham, Canada"],"countries":["CA"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":98000,"max_usd":178000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":16},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"UVM","optional":false},{"name":"Python","optional":true},{"name":"SystemVerilog","optional":true},{"name":"Verilog","optional":true}],"status":"closed","first_seen_at":"2026-08-27T16:22:00Z","employer_posted_date":"2026-10-20","last_verified_at":"2026-10-23T22:32:24Z","board_verified":false,"closed_at":"2026-10-23T22:32:24Z","days_open":57,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":57},"description":"ADVANCE YOUR CAREER. ADVANCE THE WORLD.\nAt AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.\nWhether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Join us and, together, we’ll advance your career.\n THE ROLE:\nAs a Lead Verification Engineer in the AECG Group, you will help bring to life cutting-edge FPGA, ASICs for variety of target customers. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, PD teams, and product engineers to achieve first pass silicon success.\nTHE PERSON:\nYou have a passion for modern, complex IP architectures, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.\nKEY RESPONSIBLITIES:\nCollaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified \nDevelop test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases\nCode IP or SS level UVM based testbenches, verification components - monitors, scoreboard, checkers\nBuild the directed and random verification tests \nRun regressions, debug test failures towards ensuring high design functional, performance and implementation quality \nPREFERRED EXPERIENCE:\nProficient in IP level ASIC verification\nExpert in Verilog, System Verilog, Object Oriented programming\nExpert in developing UVM based verification frameworks and testbenches \nScripting and automation of verification processes and flows \nExposure to simulation profile, efficiency improvement, acceleration, HLS tools/process\nGood Computer Architecture, systems knowledge\nComfortable in python / perl and editing / maintaining scripts\nExposure to leadership or mentorship is an asset \nExperience working in a team environment through the ASIC Project lifecycle from Planning to Tape Out\nExperience with PCIe, CXL, NVMe or ethernet protocols\nStrong communication skills and the ability to work independently as well as in a cross-site team environment\nACADEMIC CREDENTIALS:\nBachelors or Masters degree in computer engineering/Electrical Engineering\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.\nTHE ROLE:\nAs a Lead Verification Engineer in the AECG Group, you will help bring to life cutting-edge FPGA, ASICs for variety of target customers. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, PD teams, and product engineers to achieve first pass silicon success.\nTHE PERSON:\nYou have a passion for modern, complex IP architectures, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.\nKEY RESPONSIBLITIES:\nCollaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified \nDevelop test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases\nCode IP or SS level UVM based testbenches, verification components - monitors, scoreboard, checkers\nBuild the directed and random verification tests \nRun regressions, debug test failures towards ensuring high design functional, performance and implementation quality \nPREFERRED EXPERIENCE:\nProficient in IP level ASIC verification\nExpert in Verilog, System Verilog, Object Oriented programming\nExpert in developing UVM based verification frameworks and testbenches \nScripting and automation of verification processes and flows \nExposure to simulation profile, efficiency improvement, acceleration, HLS tools/process\nGood Computer Architecture, systems knowledge\nComfortable in python / perl and editing / maintaining scripts\nExposure to leadership or mentorship is an asset \nExperience working in a team environment through the ASIC Project lifecycle from Planning to Tape Out\nExperience with PCIe, CXL, NVMe or ethernet protocols\nStrong communication skills and the ability to work independently as well as in a cross-site team environment\nACADEMIC CREDENTIALS:\nBachelors or Masters degree in computer engineering/Electrical Engineering\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.","description_format":"text","description_chars":6709,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Computer Components","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-10-20T09:36:36Z"},{"event":"close","at":"2026-10-23T22:32:24Z"}],"visa":[],"liveness":null,"pay":null,"html_url":"https://alion.io/job/amd-lead-ip-verification-engineer-2","json_url":"https://alion.io/job/amd-lead-ip-verification-engineer-2.json","meta":{"generated_at":"2026-10-26T04:16:43Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":5878,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-27T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":93},"rest":"https://alion.io/mcp/rest/get_company?id=93"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Famd-lead-ip-verification-engineer-2"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Famd-lead-ip-verification-engineer-2"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Famd-lead-ip-verification-engineer-2"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/amd-lead-ip-verification-engineer-2\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Famd-lead-ip-verification-engineer-2"}]}