{"id":2910631,"url":"https://alion.io/job/amd-lead-physical-design-engineer-place-route","title":"Lead Physical Design Engineer, Place & Route","company":{"id":93,"name":"AMD","domain":"amd.com","url":"https://alion.io/company/amd","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Jibe","truth_index":{"grade":"B","score":75,"open_postings":163,"ghost_share":0,"stale_share":0.994,"repost_share":0,"time_to_fill_p50_days":28,"computed_at":"2026-10-24T06:02:35Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Markham, Canada"],"countries":["CA"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":89000,"max_usd":164000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":91},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":true},{"name":"Synopsys Fusion Compiler","optional":true}],"status":"live","first_seen_at":"2026-09-30T15:36:00Z","employer_posted_date":"2026-10-20","last_verified_at":"2026-10-24T18:45:49Z","board_verified":true,"closed_at":null,"days_open":24,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":24},"description":"ADVANCE YOUR CAREER. ADVANCE THE WORLD.\nAt AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.\nWhether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Join us and, together, we’ll advance your career.\n THE ROLE:\nJoin the GPU Technologies and Engineering team developing leading-edge AI and high-performance computing products on advanced process technologies. As a Senior Physical Design Engineer, you will lead physical implementation activities for complex designs, driving place-and-route execution from floorplanning through signoff. You will provide technical leadership throughout the implementation process, driving timing and congestion closure, ensuring design quality, and resolving challenging physical design issues. This role offers broad ownership, significant technical impact, and the opportunity to help deliver some of AMD's most advanced AI and graphics products.\nTHE PERSON:\nYou are a hands-on physical design engineer with deep expertise in place-and-route and physical implementation. You excel at solving complex design challenges, driving implementation quality, and bringing difficult designs to closure. You are comfortable providing technical direction, identifying risks early, and guiding implementation efforts across complex projects. The ideal candidate combines strong technical depth, sound engineering judgment, and a passion for delivering high-performance silicon.\nKEY RESPONSIBLITIES:\nLead place-and-route execution from floorplanning through signoff.\nDrive timing, congestion, and power closure for complex designs.\nDevelop and optimize floorplanning, placement, clock tree, and routing strategies.\nIdentify and resolve critical physical design and implementation issues.\nPerform timing analysis, parasitic extraction, and power integrity analysis.\nExecute physical verification and signoff activities, including ERC and LVS.\nProvide technical guidance and drive implementation quality across design activities.\nPartner with architecture, design, integration, and product engineering teams to deliver successful silicon.\nEnhance physical design methodologies, automation, and implementation flows.\nPREFERRED EXPERIENCE:\nExperience with ASIC physical design and implementation flows.\nStrong expertise in place-and-route methodologies for complex designs.\nExperience with floorplanning, placement, clock tree synthesis, routing, and timing closure.\nExperience resolving timing, congestion, power, and signal integrity challenges.\nExperience with physical verification and signoff methodologies, including ERC and LVS.\nExperience with advanced-node and high-speed design implementations.\nProficiency with Synopsys Fusion Compiler, Cadence, and Siemens EDA tools.\nExperience with TCL, Perl, or Shell scripting for design automation and flow development.\nExperience providing technical leadership across physical design activities.\nACADEMIC CREDENTIALS:\nBachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field preferred.\n\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.\nTHE ROLE:\nJoin the GPU Technologies and Engineering team developing leading-edge AI and high-performance computing products on advanced process technologies. As a Senior Physical Design Engineer, you will lead physical implementation activities for complex designs, driving place-and-route execution from floorplanning through signoff. You will provide technical leadership throughout the implementation process, driving timing and congestion closure, ensuring design quality, and resolving challenging physical design issues. This role offers broad ownership, significant technical impact, and the opportunity to help deliver some of AMD's most advanced AI and graphics products.\nTHE PERSON:\nYou are a hands-on physical design engineer with deep expertise in place-and-route and physical implementation. You excel at solving complex design challenges, driving implementation quality, and bringing difficult designs to closure. You are comfortable providing technical direction, identifying risks early, and guiding implementation efforts across complex projects. The ideal candidate combines strong technical depth, sound engineering judgment, and a passion for delivering high-performance silicon.\nKEY RESPONSIBLITIES:\nLead place-and-route execution from floorplanning through signoff.\nDrive timing, congestion, and power closure for complex designs.\nDevelop and optimize floorplanning, placement, clock tree, and routing strategies.\nIdentify and resolve critical physical design and implementation issues.\nPerform timing analysis, parasitic extraction, and power integrity analysis.\nExecute physical verification and signoff activities, including ERC and LVS.\nProvide technical guidance and drive implementation quality across design activities.\nPartner with architecture, design, integration, and product engineering teams to deliver successful silicon.\nEnhance physical design methodologies, automation, and implementation flows.\nPREFERRED EXPERIENCE:\nExperience with ASIC physical design and implementation flows.\nStrong expertise in place-and-route methodologies for complex designs.\nExperience with floorplanning, placement, clock tree synthesis, routing, and timing closure.\nExperience resolving timing, congestion, power, and signal integrity challenges.\nExperience with physical verification and signoff methodologies, including ERC and LVS.\nExperience with advanced-node and high-speed design implementations.\nProficiency with Synopsys Fusion Compiler, Cadence, and Siemens EDA tools.\nExperience with TCL, Perl, or Shell scripting for design automation and flow development.\nExperience providing technical leadership across physical design activities.\nACADEMIC CREDENTIALS:\nBachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field preferred.\n\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.","description_format":"text","description_chars":8073,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Computer Components","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-10-20T09:28:01Z"}],"visa":[],"liveness":{"score":45,"band":"ok","label":"Likely open","p_open":1,"p_active":0.601,"p_room":0.75,"age_days":23,"expected_fill_days":28,"reasons":["conf:3","stale_co","velocity","win:late","comp:brand"],"computed_at":"2026-10-24T06:02:35Z"},"pay":null,"html_url":"https://alion.io/job/amd-lead-physical-design-engineer-place-route","json_url":"https://alion.io/job/amd-lead-physical-design-engineer-place-route.json","meta":{"generated_at":"2026-10-24T21:23:16Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":31387,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-25T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":93},"rest":"https://alion.io/mcp/rest/get_company?id=93"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Famd-lead-physical-design-engineer-place-route"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Famd-lead-physical-design-engineer-place-route"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Famd-lead-physical-design-engineer-place-route"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/amd-lead-physical-design-engineer-place-route\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Famd-lead-physical-design-engineer-place-route"}]}