{"id":2910095,"url":"https://alion.io/job/amd-memory-phy-principal-design-engineer","title":"Memory PHY Principal Design Engineer","company":{"id":93,"name":"AMD","domain":"amd.com","url":"https://alion.io/company/amd","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Jibe","truth_index":{"grade":"B","score":80,"open_postings":160,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":20,"computed_at":"2026-10-23T05:54:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Santa Clara, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":168000,"max_usd":319000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":609},"experience_years_min":null,"visa_sponsorship":true,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":true},{"name":"Python","optional":true},{"name":"SystemVerilog","optional":true},{"name":"Verilog","optional":true}],"status":"live","first_seen_at":"2026-10-09T21:40:00Z","employer_posted_date":"2026-10-20","last_verified_at":"2026-10-23T13:34:26Z","board_verified":true,"closed_at":null,"days_open":13,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":13},"description":"ADVANCE YOUR CAREER. ADVANCE THE WORLD.\nAt AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.\nWhether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Join us and, together, we’ll advance your career.\nTHE ROLE:\nThe Memory PHY team is seeking a seasoned Memory PHY Design Engineer to help architect and develop industry-leading high-speed memory interface IP. In this role, you will shape digital PHY architecture, RTL, and firmware for LPDDR and DDR technologies while partnering closely with analog, circuit, verification, firmware, physical design, and system architecture teams. You will influence product direction, advance power, performance, and area goals, and help establish design methodologies that improve quality and execution across multiple programs.\nTHE PERSON:\nYou are a collaborative technical leader with deep curiosity about memory processor architecture, digital design, and high-speed interfaces. You communicate clearly across functions and geographies, bring structure to complex technical decisions, and build alignment among senior stakeholders. You combine strong analytical judgment with attention to detail, mentor engineers effectively, and remain comfortable learning, challenging assumptions, and guiding teams through ambiguous design problems.\nKEY RESPONSIBILITIES:\nDefine product features and capabilities, translate architecture and microarchitecture requirements into technical specifications, and provide technical direction to execution teams. \nLead Memory PHY digital architecture development from pathfinding and microarchitecture through RTL implementation, verification, and physical realization. \nArchitect and implement PHY link-layer functionality in partnership with analog and system architects. \nDrive analog and digital co-design, digital logic development, RTL coding, and firmware integration for high-speed memory interfaces. \nGuide synthesis, static timing analysis, timing closure, power optimization, and physical implementation to achieve power, performance, and area targets. \nCollaborate with architecture, hardware, verification, firmware, and physical design teams to define, implement, and validate new product features. \nIdentify complex technical issues and risks across IP and domain boundaries, then drive architectural solutions that meet product requirements. \nContribute technical knowledge, design guidance, and reusable methodologies across platform and system architecture teams. \nSupport post-silicon teams in debugging and resolving functional, performance, and power issues. \nAdvance AI-assisted design, verification, debug, and productivity methodologies to improve engineering efficiency, design quality, and time to market. \nPREFERRED EXPERIENCE:\nDeep expertise in Memory PHY architecture and implementation, including LPDDR, DDR, GDDR, HBM, SerDes, memory controllers, or other high-speed I/O subsystems. \nExpert proficiency in Verilog or SystemVerilog, digital design methodologies, and scripting languages such as Python, Perl, or Tcl. \nStrong experience with mixed-signal integration, clocking architectures, clock-domain and reset-domain crossing methodologies, low-power design, UPF, synthesis, static timing analysis, timing closure, and silicon bring-up. \nDemonstrated expertise in power-management microarchitecture, low-power design, and power optimization across architecture, logic, and circuit levels. \nExperience guiding technical direction across multiple teams and organizations while building consensus among senior stakeholders. \nProven ability to mentor engineers, share technical knowledge, and strengthen engineering practices across an organization. \nStrong communication and presentation skills, with the ability to collaborate effectively across disciplines, sites, and time zones. \nACADEMIC CREDENTIALS:\nA bachelor’s, master’s, or doctoral degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field is preferred.\nThis role is not eligible for visa sponsorship.\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.\nTHE ROLE:\nThe Memory PHY team is seeking a seasoned Memory PHY Design Engineer to help architect and develop industry-leading high-speed memory interface IP. In this role, you will shape digital PHY architecture, RTL, and firmware for LPDDR and DDR technologies while partnering closely with analog, circuit, verification, firmware, physical design, and system architecture teams. You will influence product direction, advance power, performance, and area goals, and help establish design methodologies that improve quality and execution across multiple programs.\nTHE PERSON:\nYou are a collaborative technical leader with deep curiosity about memory processor architecture, digital design, and high-speed interfaces. You communicate clearly across functions and geographies, bring structure to complex technical decisions, and build alignment among senior stakeholders. You combine strong analytical judgment with attention to detail, mentor engineers effectively, and remain comfortable learning, challenging assumptions, and guiding teams through ambiguous design problems.\nKEY RESPONSIBILITIES:\nDefine product features and capabilities, translate architecture and microarchitecture requirements into technical specifications, and provide technical direction to execution teams. \nLead Memory PHY digital architecture development from pathfinding and microarchitecture through RTL implementation, verification, and physical realization. \nArchitect and implement PHY link-layer functionality in partnership with analog and system architects. \nDrive analog and digital co-design, digital logic development, RTL coding, and firmware integration for high-speed memory interfaces. \nGuide synthesis, static timing analysis, timing closure, power optimization, and physical implementation to achieve power, performance, and area targets. \nCollaborate with architecture, hardware, verification, firmware, and physical design teams to define, implement, and validate new product features. \nIdentify complex technical issues and risks across IP and domain boundaries, then drive architectural solutions that meet product requirements. \nContribute technical knowledge, design guidance, and reusable methodologies across platform and system architecture teams. \nSupport post-silicon teams in debugging and resolving functional, performance, and power issues. \nAdvance AI-assisted design, verification, debug, and productivity methodologies to improve engineering efficiency, design quality, and time to market. \nPREFERRED EXPERIENCE:\nDeep expertise in Memory PHY architecture and implementation, including LPDDR, DDR, GDDR, HBM, SerDes, memory controllers, or other high-speed I/O subsystems. \nExpert proficiency in Verilog or SystemVerilog, digital design methodologies, and scripting languages such as Python, Perl, or Tcl. \nStrong experience with mixed-signal integration, clocking architectures, clock-domain and reset-domain crossing methodologies, low-power design, UPF, synthesis, static timing analysis, timing closure, and silicon bring-up. \nDemonstrated expertise in power-management microarchitecture, low-power design, and power optimization across architecture, logic, and circuit levels. \nExperience guiding technical direction across multiple teams and organizations while building consensus among senior stakeholders. \nProven ability to mentor engineers, share technical knowledge, and strengthen engineering practices across an organization. \nStrong communication and presentation skills, with the ability to collaborate effectively across disciplines, sites, and time zones. \nACADEMIC CREDENTIALS:\nA bachelor’s, master’s, or doctoral degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field is preferred.\nThis role is not eligible for visa sponsorship.\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. 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