{"id":2910208,"url":"https://alion.io/job/amd-pd-cad-engineer","title":"PD CAD Engineer","company":{"id":93,"name":"AMD","domain":"amd.com","url":"https://alion.io/company/amd","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Jibe","truth_index":{"grade":"B","score":75,"open_postings":163,"ghost_share":0,"stale_share":0.994,"repost_share":0,"time_to_fill_p50_days":28,"computed_at":"2026-10-24T06:02:35Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"middle","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hyderabad, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":4,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Innovus","optional":true},{"name":"Python","optional":true}],"status":"live","first_seen_at":"2026-10-07T06:38:00Z","employer_posted_date":"2026-10-20","last_verified_at":"2026-10-24T11:15:48Z","board_verified":true,"closed_at":null,"days_open":17,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":17},"description":"ADVANCE YOUR CAREER. ADVANCE THE WORLD.\nAt AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.\nWhether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Join us and, together, we’ll advance your career.\nSDE CAD SILICON DESIGN ENGINEER:\nTHE ROLE:\nThis position for a CAD Engineer will be critical to shaping the next generation AMD products, the leader in GPU, CPU. It requires interfacing with large design teams across the globe and owning development & support for next generation synthesis, place and route flows. Successful candidate would be responsible for automation of PnR flows and methodologies for the 3nm & 2nm technology nodes as well as working closely with the EDA vendors to identify innovative solutions and track methodology issues.\nTHE PERSON:\nYou have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems\nKEY RESPONSIBILITIES:\nResponsible for developing Place and Route methodologies for various designs at advanced technology nodes\nWork seamlessly with synthesis and signoff (STA, extraction, Physical Verification) teams to achieve best-in-class PPA\nDrive power/performance/area (PPA) convergence for SOCs implementation\nScript out utilities to automate different pieces of the implementation flow\nSupport design teams at global sites through multiple PnR flow stages including chip finish flows\nCAD flow and Methodology development on advanced process nodes such as 3nm, 2nm are preferred\nPREFERRED EXPERIENCE:\nHands-on experience in PNR flows including multi-voltage & power-gated designs \nExpertise with industry-standard physical design tools Cadence Innovus\nExperience with synthesis, STA, Physical verification domains is a plus\nStrong understanding of low-power flows includes UPF concepts, power-gating, isolation, level-shifter, voltage_areas, power-state tables, electrical checks FM & VSI\nProficiency in scripting and automation using Python, TCL with strong debugging capabilities and CAD-automation mindset. \nExposure to AI/ML concepts, with strong Python proficiency.\nCAD and Automation mindset\nACADEMIC CREDENTIALS:\nMaster’s/Bachelor’s Degree in Electronics Engineering (Minor in Computer Science preferred)\n4-6 years of experience in CAD flow and methodology development on advanced nodes such as 3nm & 2nm\nWork closely with design teams to support multiple areas through Netlist to GDSII implementation\nSupport cross site design teams at various global sites\nStrong problem-solving skills and analytical thinking\nTeam player, good work ethic, and excellent communication skills\nLocation: AMD Hyderabad/\n#LI-BM2\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.\nSDE CAD SILICON DESIGN ENGINEER:\nTHE ROLE:\nThis position for a CAD Engineer will be critical to shaping the next generation AMD products, the leader in GPU, CPU. It requires interfacing with large design teams across the globe and owning development & support for next generation synthesis, place and route flows. Successful candidate would be responsible for automation of PnR flows and methodologies for the 3nm & 2nm technology nodes as well as working closely with the EDA vendors to identify innovative solutions and track methodology issues.\nTHE PERSON:\nYou have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems\nKEY RESPONSIBILITIES:\nResponsible for developing Place and Route methodologies for various designs at advanced technology nodes\nWork seamlessly with synthesis and signoff (STA, extraction, Physical Verification) teams to achieve best-in-class PPA\nDrive power/performance/area (PPA) convergence for SOCs implementation\nScript out utilities to automate different pieces of the implementation flow\nSupport design teams at global sites through multiple PnR flow stages including chip finish flows\nCAD flow and Methodology development on advanced process nodes such as 3nm, 2nm are preferred\nPREFERRED EXPERIENCE:\nHands-on experience in PNR flows including multi-voltage & power-gated designs \nExpertise with industry-standard physical design tools Cadence Innovus\nExperience with synthesis, STA, Physical verification domains is a plus\nStrong understanding of low-power flows includes UPF concepts, power-gating, isolation, level-shifter, voltage_areas, power-state tables, electrical checks FM & VSI\nProficiency in scripting and automation using Python, TCL with strong debugging capabilities and CAD-automation mindset. \nExposure to AI/ML concepts, with strong Python proficiency.\nCAD and Automation mindset\nACADEMIC CREDENTIALS:\nMaster’s/Bachelor’s Degree in Electronics Engineering (Minor in Computer Science preferred)\n4-6 years of experience in CAD flow and methodology development on advanced nodes such as 3nm & 2nm\nWork closely with design teams to support multiple areas through Netlist to GDSII implementation\nSupport cross site design teams at various global sites\nStrong problem-solving skills and analytical thinking\nTeam player, good work ethic, and excellent communication skills\nLocation: AMD Hyderabad/\n#LI-BM2\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.","description_format":"text","description_chars":7764,"description_truncated":false,"requirements":{"experience_years_min":4,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":true},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Computer Components","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-10-20T09:19:33Z"}],"visa":[],"liveness":{"score":52,"band":"ok","label":"Likely open","p_open":1,"p_active":0.578,"p_room":0.9,"age_days":16,"expected_fill_days":28,"reasons":["conf:3","stale_co","velocity","win:mid","comp:brand"],"computed_at":"2026-10-24T06:02:35Z"},"pay":null,"html_url":"https://alion.io/job/amd-pd-cad-engineer","json_url":"https://alion.io/job/amd-pd-cad-engineer.json","meta":{"generated_at":"2026-10-24T12:32:16Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":18021,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-25T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":93},"rest":"https://alion.io/mcp/rest/get_company?id=93"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Famd-pd-cad-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Famd-pd-cad-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Famd-pd-cad-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/amd-pd-cad-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Famd-pd-cad-engineer"}]}