{"id":2910686,"url":"https://alion.io/job/amd-pd-clocking-engineer","title":"PD Clocking Engineer","company":{"id":93,"name":"AMD","domain":"amd.com","url":"https://alion.io/company/amd","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Jibe","truth_index":{"grade":"A","score":95,"open_postings":10,"ghost_share":0,"stale_share":0.2,"repost_share":0,"time_to_fill_p50_days":42,"computed_at":"2026-11-04T06:34:25Z"}},"role":"Hardware","role_family":"Hardware","seniority":null,"employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Ansys RedHawk","optional":false},{"name":"Python","optional":false},{"name":"Siemens Calibre","optional":false},{"name":"Synopsys Fusion Compiler","optional":false},{"name":"Synopsys PrimeTime","optional":false}],"status":"live","first_seen_at":"2026-09-28T06:24:00Z","employer_posted_date":"2026-11-04","last_verified_at":"2026-11-04T06:53:24Z","board_verified":true,"closed_at":null,"days_open":37,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":37},"description":"ADVANCE YOUR CAREER. ADVANCE THE WORLD.\nAt AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.\nWhether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Join us and, together, we’ll advance your career.\nRole Summary\nOwn and drive clocking and Physical Design (PnR) methodologies for complex SoC/ASIC designs. Responsible for developing, validating, and maintaining implementation flows, clock-tree methodologies, timing correlation, QoR convergence strategies, and automation frameworks used across multiple projects.\nKey Responsibilities\nOwn end-to-end clocking methodology including CTS architecture, clock latency/skew management, clock QoR reviews, and timing convergence strategies.\nDevelop, certify, and maintain PnR implementation flows across technology nodes and design styles. \nDrive flow correlation between Tile PnR, Full-Chip Timing (FCT), STA, and signoff environments to ensure predictable closure.\nDefine implementation recipes, optimisation strategies, and best practices for timing, congestion, power, and area closure. \nDevelop automation using Tcl/Python/Shell to improve productivity, debug efficiency, and flow robustness. \nPartner with CAD, FCFP, Timing, DFT, and Design teams to resolve methodology issues and improve project execution. \nEnable new technology nodes, validate EDA tool features, and drive methodology enhancements for future projects\nRequired Qualifications\nBachelor's/Master's degree in Electrical/Electronics Engineering.\nStrong understanding of ASIC Physical Design flow including Floorplanning, Placement, CTS, Routing, STA, ECO, IR/EM, and Physical Verification.\nExpertise in clock-tree synthesis, clock skew/latency optimisation, and timing closure methodologies.\nExperience with industry-standard tools such as Fusion Compiler, ICC2, Innovus, PrimeTime, Calibre, and RedHawk.\nStrong scripting skills in Tcl, Python, and Shell.\nGood debugging, problem-solving, and cross-functional collaboration skills.\nPreferred Experience\nPrior experience owning flow development, methodology certification, or automation projects.\nExperience across advanced technology nodes (5nm/3nm and below) is a plus.\n#LI-BM2\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.\nRole Summary\nOwn and drive clocking and Physical Design (PnR) methodologies for complex SoC/ASIC designs. Responsible for developing, validating, and maintaining implementation flows, clock-tree methodologies, timing correlation, QoR convergence strategies, and automation frameworks used across multiple projects.\nKey Responsibilities\nOwn end-to-end clocking methodology including CTS architecture, clock latency/skew management, clock QoR reviews, and timing convergence strategies.\nDevelop, certify, and maintain PnR implementation flows across technology nodes and design styles. \nDrive flow correlation between Tile PnR, Full-Chip Timing (FCT), STA, and signoff environments to ensure predictable closure.\nDefine implementation recipes, optimisation strategies, and best practices for timing, congestion, power, and area closure. \nDevelop automation using Tcl/Python/Shell to improve productivity, debug efficiency, and flow robustness. \nPartner with CAD, FCFP, Timing, DFT, and Design teams to resolve methodology issues and improve project execution. \nEnable new technology nodes, validate EDA tool features, and drive methodology enhancements for future projects\nRequired Qualifications\nBachelor's/Master's degree in Electrical/Electronics Engineering.\nStrong understanding of ASIC Physical Design flow including Floorplanning, Placement, CTS, Routing, STA, ECO, IR/EM, and Physical Verification.\nExpertise in clock-tree synthesis, clock skew/latency optimisation, and timing closure methodologies.\nExperience with industry-standard tools such as Fusion Compiler, ICC2, Innovus, PrimeTime, Calibre, and RedHawk.\nStrong scripting skills in Tcl, Python, and Shell.\nGood debugging, problem-solving, and cross-functional collaboration skills.\nPreferred Experience\nPrior experience owning flow development, methodology certification, or automation projects.\nExperience across advanced technology nodes (5nm/3nm and below) is a plus.\n#LI-BM2\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. 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