{"id":2912036,"url":"https://alion.io/job/amd-performance-modeling-and-optimization-engineering-director","title":"Performance Modeling and Optimization Engineering Director","company":{"id":93,"name":"AMD","domain":"amd.com","url":"https://alion.io/company/amd","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Jibe","truth_index":null},"role":"Leadership","role_family":"Leadership","seniority":"head","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":64000,"max_usd":156000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":49},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Platform Engineering","optional":false}],"status":"live","first_seen_at":"2026-07-06T16:34:00Z","employer_posted_date":"2026-10-20","last_verified_at":"2026-10-21T02:27:25Z","board_verified":true,"closed_at":null,"days_open":106,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":106},"description":"WHAT YOU DO AT AMD CHANGES EVERYTHING\nAt AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gamingand embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuityand a shared passion to create something extraordinary. When you join AMD, you’lldiscover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.Together, we advance your career.\nPerformance Modeling and Optimization Engineering Director:\nTHE ROLE\nThe Director is responsible for owning end to end silicon (i.e., pre - post silicon) performance and design execution. This role provides technical and organizational leadership for system-level performance attainment, hardware/software optimizations, silicon debug, and sustained performance delivery for complex SoCs and accelerators. The Director drives cross functional alignment across architecture, modeling, design, validation, software, and product teams to ensure performance, power, and efficiency targets are met for current and future products.\nTHE PERSON\nIn this role you would manage a global organization of ~30+ engineers, with growth potential to 50+.\nDirect impact on product competitiveness, customer performance outcomes, and long-term silicon roadmap success.\nKEY RESPONSIBILITIES\nTechnical Leadership\nOwn system level performance attainment and HW/SW optimization to improve out of box and sustained performance across silicon products. \nLead post-silicon debug, regression, performance analysis, and optimization efforts to achieve committed product targets. \nEstablish and evolve methodologies for power and performance modeling, validation, and silicon bring up. \nExecution & Delivery\nLead execution across multiple silicon programs, ensuring performance and power goals are met on schedule. \nPartner closely with architecture, RTL design, verification, firmware, system software, and product management teams. \nIdentify and mitigate technical and execution risks across the silicon lifecycle. \nDrive continuous improvement in tools, flows, and best practices for silicon design and performance engineering. \nPeople & Organizational Leadership\nBuild, scale, and lead a global team of silicon design and performance engineers. \nManage senior technical leaders (Fellows, Senior Fellows, Directors) and develop succession plans. \nSet clear technical direction, performance expectations, and career development paths for the organization. \nFoster a culture of technical excellence, accountability, and collaboration. \nCross Functional & External Engagement\nServe as a primary technical interface with internal senior leadership, including Directors, Senior Directors, Fellows, and Engineering VPs. \nEngage externally with customer platform engineering teams, engineering leads, and product stakeholders as needed. \nRepresent silicon design and performance perspectives in executive reviews and customer engagements. \nPREFERRED EXPERIENCE:\nExtensive experience in silicon design engineering, performance architecture, or related technical domains. \nDeep understanding of SoC architecture, performance modeling, power analysis, and silicon debug. \nProven experience leading large, global engineering teams. \nStrong cross functional leadership and communication skills. \nDemonstrated ability to drive complex technical programs from concept through post silicon execution. \nExperience with high performance compute, AI accelerators, GPUs, or largescale SoCs. \nBackground in both hardware and system/software performance optimization. \nPrior experience interfacing with external customers or partners on silicon performance topics. \nACADEMIC CREDENTIALS:\nBachelor’s or master’s degree in electrical or computer engineering \nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.\nPerformance Modeling and Optimization Engineering Director:\nTHE ROLE\nThe Director is responsible for owning end to end silicon (i.e., pre - post silicon) performance and design execution. This role provides technical and organizational leadership for system-level performance attainment, hardware/software optimizations, silicon debug, and sustained performance delivery for complex SoCs and accelerators. The Director drives cross functional alignment across architecture, modeling, design, validation, software, and product teams to ensure performance, power, and efficiency targets are met for current and future products.\nTHE PERSON\nIn this role you would manage a global organization of ~30+ engineers, with growth potential to 50+.\nDirect impact on product competitiveness, customer performance outcomes, and long-term silicon roadmap success.\nKEY RESPONSIBILITIES\nTechnical Leadership\nOwn system level performance attainment and HW/SW optimization to improve out of box and sustained performance across silicon products. \nLead post-silicon debug, regression, performance analysis, and optimization efforts to achieve committed product targets. \nEstablish and evolve methodologies for power and performance modeling, validation, and silicon bring up. \nExecution & Delivery\nLead execution across multiple silicon programs, ensuring performance and power goals are met on schedule. \nPartner closely with architecture, RTL design, verification, firmware, system software, and product management teams. \nIdentify and mitigate technical and execution risks across the silicon lifecycle. \nDrive continuous improvement in tools, flows, and best practices for silicon design and performance engineering. \nPeople & Organizational Leadership\nBuild, scale, and lead a global team of silicon design and performance engineers. \nManage senior technical leaders (Fellows, Senior Fellows, Directors) and develop succession plans. \nSet clear technical direction, performance expectations, and career development paths for the organization. \nFoster a culture of technical excellence, accountability, and collaboration. \nCross Functional & External Engagement\nServe as a primary technical interface with internal senior leadership, including Directors, Senior Directors, Fellows, and Engineering VPs. \nEngage externally with customer platform engineering teams, engineering leads, and product stakeholders as needed. \nRepresent silicon design and performance perspectives in executive reviews and customer engagements. \nPREFERRED EXPERIENCE:\nExtensive experience in silicon design engineering, performance architecture, or related technical domains. \nDeep understanding of SoC architecture, performance modeling, power analysis, and silicon debug. \nProven experience leading large, global engineering teams. \nStrong cross functional leadership and communication skills. \nDemonstrated ability to drive complex technical programs from concept through post silicon execution. \nExperience with high performance compute, AI accelerators, GPUs, or largescale SoCs. \nBackground in both hardware and system/software performance optimization. \nPrior experience interfacing with external customers or partners on silicon performance topics. \nACADEMIC CREDENTIALS:\nBachelor’s or master’s degree in electrical or computer engineering \nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.","description_format":"text","description_chars":9261,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Computer Components","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-10-20T09:44:57Z"}],"visa":[],"liveness":{"score":10,"band":"cold","label":"Long shot","p_open":1,"p_active":0.368,"p_room":0.28,"age_days":106,"expected_fill_days":14,"reasons":["conf:0","win:tail","crowd:brand"],"computed_at":"2026-10-21T03:10:09Z"},"pay":null,"html_url":"https://alion.io/job/amd-performance-modeling-and-optimization-engineering-director","json_url":"https://alion.io/job/amd-performance-modeling-and-optimization-engineering-director.json","meta":{"generated_at":"2026-10-21T03:10:09Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":4720,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-22T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":93},"rest":"https://alion.io/mcp/rest/get_company?id=93"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Famd-performance-modeling-and-optimization-engineering-director"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Famd-performance-modeling-and-optimization-engineering-director"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Famd-performance-modeling-and-optimization-engineering-director"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/amd-performance-modeling-and-optimization-engineering-director\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Famd-performance-modeling-and-optimization-engineering-director"}]}