{"id":2912214,"url":"https://alion.io/job/amd-physical-design-engineer-4","title":"Physical Design Engineer","company":{"id":93,"name":"AMD","domain":"amd.com","url":"https://alion.io/company/amd","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Jibe","truth_index":{"grade":"B","score":80,"open_postings":157,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":15,"computed_at":"2026-10-22T06:10:10Z"}},"role":"Hardware","role_family":"Hardware","seniority":null,"employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Vancouver, Canada"],"countries":["CA"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":69000,"max_usd":137000,"period":"year","method":"role_country_seniority_unknown","sample_n":146},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Verilog","optional":true}],"status":"live","first_seen_at":"2026-06-15T19:15:00Z","employer_posted_date":"2026-10-20","last_verified_at":"2026-10-22T19:30:57Z","board_verified":true,"closed_at":null,"days_open":129,"trust":{"level":"stale","repost_count":0,"flags":["stale"],"days_open":128},"description":"WHAT YOU DO AT AMD CHANGES EVERYTHING\nAt AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gamingand embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuityand a shared passion to create something extraordinary. When you join AMD, you’lldiscover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.Together, we advance your career.\n THE ROLE:\nIn this role, you will play a critical part in shaping AMD’s next-generation graphics processor IP by driving best-in-class Performance, Power, and Area (PPA) outcomes. You will partner closely with RTL, Physical Design, Methodology, and CAD teams to translate innovative architectures into high-quality silicon, influencing design decisions early and throughout the execution cycle. This is a highly visible, hands-on role where your technical leadership and insight will directly impact product success from concept to tape-out.\nTHE PERSON:\nYou are passionate about modern processor architectures and bring a collaborative, analytical, and detail-oriented approach to complex design challenges. You communicate clearly across disciplines and time zones, take strong ownership of your work, and are comfortable navigating ambiguity while driving results. You value teamwork, proactively identify risks and opportunities, and enjoy mentoring others while contributing to a culture of technical excellence, continuous learning, and mutual respect.\nKEY RESPONSIBILITIES:\nLead engineer driving PPA improvements for critical graphics blocks, and serves as main point of contact from Physical Design to RTL teams. \nStudy block microarchitecture and data flow to determine optimal memory placement & Synthesis/P&R Recipes.\nWork with RTL design to understand upcoming feature changes and resolve potential bottlenecks for frequency, LOL and timing issues early in the project cycle.\nCollaborate with RTL designers to explore additional opportunities for area and power savings.\nPartner with Methodology and CAD teams to optimize tools/flows for achieving best in class PPA. \nDeliver best known recipes to PD tile owners for achieving Performance, Power and Area targets. \nAnalyze stdcell library offerings and work with library team to evaluate PPA impact/benefit from different standard cell offerings.\nPREFERRED EXPERIENCE:\nExperience in ASIC Physical Design from RTL to GDSII.\nStrong RTL analysis skills including Verilog, Timing Analysis, and library understanding.\nStrong knowledge in design margining methodology, low voltage design, silicon - STA correlation.\nHands on experience in taping out 3nm, 5nm, 7nm and/or 16nm SOC.\nWorking experience on CAD tools from Synopsys, Cadence and Mentor Graphics.\nStrong communication, time management, and presentation skills.\nExcellent analytical, problem solving, and attention to detail skills.\nMust be a self-starter, and be able to independently and efficiently drive tasks to completion.\nProvide mentorship and guidance to junior and senior engineers, and be an effective team player.\nACADEMIC CREDENTIALS:\nBachelors or Mastersdegree in computer engineering/Electrical Engineering\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.\nTHE ROLE:\nIn this role, you will play a critical part in shaping AMD’s next-generation graphics processor IP by driving best-in-class Performance, Power, and Area (PPA) outcomes. You will partner closely with RTL, Physical Design, Methodology, and CAD teams to translate innovative architectures into high-quality silicon, influencing design decisions early and throughout the execution cycle. This is a highly visible, hands-on role where your technical leadership and insight will directly impact product success from concept to tape-out.\nTHE PERSON:\nYou are passionate about modern processor architectures and bring a collaborative, analytical, and detail-oriented approach to complex design challenges. You communicate clearly across disciplines and time zones, take strong ownership of your work, and are comfortable navigating ambiguity while driving results. You value teamwork, proactively identify risks and opportunities, and enjoy mentoring others while contributing to a culture of technical excellence, continuous learning, and mutual respect.\nKEY RESPONSIBILITIES:\nLead engineer driving PPA improvements for critical graphics blocks, and serves as main point of contact from Physical Design to RTL teams. \nStudy block microarchitecture and data flow to determine optimal memory placement & Synthesis/P&R Recipes.\nWork with RTL design to understand upcoming feature changes and resolve potential bottlenecks for frequency, LOL and timing issues early in the project cycle.\nCollaborate with RTL designers to explore additional opportunities for area and power savings.\nPartner with Methodology and CAD teams to optimize tools/flows for achieving best in class PPA. \nDeliver best known recipes to PD tile owners for achieving Performance, Power and Area targets. \nAnalyze stdcell library offerings and work with library team to evaluate PPA impact/benefit from different standard cell offerings.\nPREFERRED EXPERIENCE:\nExperience in ASIC Physical Design from RTL to GDSII.\nStrong RTL analysis skills including Verilog, Timing Analysis, and library understanding.\nStrong knowledge in design margining methodology, low voltage design, silicon - STA correlation.\nHands on experience in taping out 3nm, 5nm, 7nm and/or 16nm SOC.\nWorking experience on CAD tools from Synopsys, Cadence and Mentor Graphics.\nStrong communication, time management, and presentation skills.\nExcellent analytical, problem solving, and attention to detail skills.\nMust be a self-starter, and be able to independently and efficiently drive tasks to completion.\nProvide mentorship and guidance to junior and senior engineers, and be an effective team player.\nACADEMIC CREDENTIALS:\nBachelors or Mastersdegree in computer engineering/Electrical Engineering\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.","description_format":"text","description_chars":8112,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":["Continuous learning"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Computer Components","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-10-20T09:52:16Z"}],"visa":[],"liveness":{"score":2,"band":"cold","label":"Long shot","p_open":1,"p_active":0.076,"p_room":0.28,"age_days":128,"expected_fill_days":15,"reasons":["conf:1","stale_co","wave","velocity","win:tail","crowd:brand"],"computed_at":"2026-10-22T06:10:10Z"},"pay":null,"html_url":"https://alion.io/job/amd-physical-design-engineer-4","json_url":"https://alion.io/job/amd-physical-design-engineer-4.json","meta":{"generated_at":"2026-10-22T21:50:32Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":6612,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-23T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":93},"rest":"https://alion.io/mcp/rest/get_company?id=93"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Famd-physical-design-engineer-4"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Famd-physical-design-engineer-4"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Famd-physical-design-engineer-4"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/amd-physical-design-engineer-4\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Famd-physical-design-engineer-4"}]}