{"id":2910579,"url":"https://alion.io/job/amd-physical-design-engineer","title":"Physical Design Engineer","company":{"id":93,"name":"AMD","domain":"amd.com","url":"https://alion.io/company/amd","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Jibe","truth_index":{"grade":"B","score":80,"open_postings":157,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":15,"computed_at":"2026-10-22T06:10:10Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"middle","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":4,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Ansys RedHawk","optional":false},{"name":"Cadence Voltus","optional":false},{"name":"Perl","optional":true},{"name":"Python","optional":true}],"status":"live","first_seen_at":"2026-10-05T07:50:00Z","employer_posted_date":"2026-10-20","last_verified_at":"2026-10-22T23:33:01Z","board_verified":true,"closed_at":null,"days_open":17,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":17},"description":"ADVANCE YOUR CAREER. ADVANCE THE WORLD.\nAt AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.\nWhether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Join us and, together, we’ll advance your career.\nPhysical Design Engineer : EMIR / PDN\nDomain: ASIC / SoC Physical Design, EMIR\nTHE ROLE:\nWe are looking for an adaptive, self-motivated Senior Silicon Design Engineer with strong experience in Electromigration and IR Drop (EMIR) analysis to join our growing team.\nAs a key contributor, you will be responsible for driving EMIR analysis, debug, and signoff closure for complex, high-performance SoC designs using industry-standard tools such as Ansys RedHawk-SC and Cadence Voltus.\nYou will collaborate closely with Physical Design, Power, Package, and other cross-functional teams to identify power integrity risks, perform root-cause analysis, recommend design improvements, and drive issues to closure.\nYou will also contribute to improving EMIR methodologies, automation, flow efficiency, and overall design quality to enable robust and reliable silicon.\nTHE PERSON:\nYou have a passion for silicon design, physical design, and solving complex EMIR challenges. You possess a strong understanding of power delivery networks and the interaction between floorplan, power grid, placement, routing, bumps, power distribution, and design activity.\nYou are a team player with excellent communication and collaboration skills and are comfortable working with engineers across different teams, sites, and time zones.\nYou have strong analytical and problem-solving skills, with the ability to independently debug complex EMIR issues, identify root causes, propose practical design solutions, and drive issues to closure.\nYou are self-motivated, willing to learn, and continuously look for opportunities to improve methodologies, automation, debug efficiency, and overall design convergence.\nKEY RESPONSIBILITIES:\nPerform static and dynamic IR-drop and Electromigration analysis using industry-standard EMIR tools such as Ansys RedHawk-SC and Cadence Voltus for complex SoC designs.\nDevelop, maintain, and validate EMIR flows and analysis setups across different stages of the physical design cycle.\nPerform power-grid validation and identify weak-grid regions, voltage-drop hotspots, current-density violations, and power connectivity issues.\nValidate EMIR database quality and input data integrity, and identify setup or data-related issues that could impact the accuracy and quality of EMIR analysis.\nPerform detailed root-cause analysis of EMIR violations and provide actionable recommendations to Physical Design and other related teams.\nWork closely with Physical Design teams to drive power-grid optimization, via enhancement, metal strengthening, floorplan updates, placement optimization, and ECO-based fixes.\nAnalyze EMIR challenges associated with voltage islands, multiple power domains, power-domain boundaries, bump distribution, and power-grid connectivity.\nIdentify critical issues early in the design cycle that may require floorplan, bump, or power-grid architecture changes.\nAnalyze results across multiple design iterations to identify new violations, regressions, and unexpected changes, and drive them toward resolution.\nWork closely with design teams to determine whether identified EMIR issues can be addressed through ECO changes or require more significant power-grid/design modifications.\nDrive assigned blocks/subsystems toward EMIR signoff and design convergence, while meeting project quality and schedule requirements.\nDevelop and improve automation for EMIR flow execution, data processing, analysis, debug, and reporting.\nCollaborate effectively with cross-functional teams and provide technical guidance and support on EMIR related issues.\nContribute to continuous improvement of EMIR methodologies, checks, best practices, and design closure processes.\nPREFERRED EXPERIENCE:\n4 +Years of hands-on experience in ASIC/SoC Physical Design with significant experience in EMIR analysis and signoff.\nStrong hands-on experience with Ansys RedHawk-SC and/or Cadence Voltus for Electromigration and IR-drop analysis. Experience with both tools is highly preferred.\nStrong understanding of Power Delivery Networks (PDN), static IR drop, dynamic IR drop, Electromigration, current density, and power-grid reliability.\nExperience with EMIR flow setup, database validation, debug, analysis, and signoff closure.\nStrong understanding of the impact of floorplan, placement, routing, power-grid design, vias, and bumps on EMIR.\nExperience in debugging EMIR violations and providing effective and practical design recommendations for issue resolution.\nGood understanding of multi-voltage designs, voltage islands, and power-domain interactions.\nExperience in power-grid robustness analysis and validation and identifying potential design weaknesses early in the implementation cycle.\nFamiliarity with physical design inputs and data such as LEF/DEF, parasitics, power/activity data, technology files, power intent, and design databases.\nGood understanding of the overall ASIC Physical Design flow from floorplanning through implementation, ECO, and signoff.\nExperience with scripting languages such as Python, Tcl, Perl, and/or Shell for flow automation, data analysis, reporting, and productivity improvement.\nExperience working on advanced-node, high-performance, or large-scale SoC designs is preferred.\nExperience with hierarchical/block-to-top EMIR analysis methodologies is an added advantage.\nExposure to chip/package power-integrity interactions, bump planning, and package-related power delivery considerations is preferred.\nAbility to independently analyze large amounts of EMIR data, identify trends and systematic issues, and drive corrective actions.\nACADEMIC CREDENTIALS:\nBachelor's or Master's degree in Electrical Engineering, Electronics Engineering, VLSI, Microelectronics, or a related discipline.#LI-SR5\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.\nPhysical Design Engineer : EMIR / PDN\nDomain: ASIC / SoC Physical Design, EMIR\nTHE ROLE:\nWe are looking for an adaptive, self-motivated Senior Silicon Design Engineer with strong experience in Electromigration and IR Drop (EMIR) analysis to join our growing team.\nAs a key contributor, you will be responsible for driving EMIR analysis, debug, and signoff closure for complex, high-performance SoC designs using industry-standard tools such as Ansys RedHawk-SC and Cadence Voltus.\nYou will collaborate closely with Physical Design, Power, Package, and other cross-functional teams to identify power integrity risks, perform root-cause analysis, recommend design improvements, and drive issues to closure.\nYou will also contribute to improving EMIR methodologies, automation, flow efficiency, and overall design quality to enable robust and reliable silicon.\nTHE PERSON:\nYou have a passion for silicon design, physical design, and solving complex EMIR challenges. You possess a strong understanding of power delivery networks and the interaction between floorplan, power grid, placement, routing, bumps, power distribution, and design activity.\nYou are a team player with excellent communication and collaboration skills and are comfortable working with engineers across different teams, sites, and time zones.\nYou have strong analytical and problem-solving skills, with the ability to independently debug complex EMIR issues, identify root causes, propose practical design solutions, and drive issues to closure.\nYou are self-motivated, willing to learn, and continuously look for opportunities to improve methodologies, automation, debug efficiency, and overall design convergence.\nKEY RESPONSIBILITIES:\nPerform static and dynamic IR-drop and Electromigration analysis using industry-standard EMIR tools such as Ansys RedHawk-SC and Cadence Voltus for complex SoC designs.\nDevelop, maintain, and validate EMIR flows and analysis setups across different stages of the physical design cycle.\nPerform power-grid validation and identify weak-grid regions, voltage-drop hotspots, current-density violations, and power connectivity issues.\nValidate EMIR database quality and input data integrity, and identify setup or data-related issues that could impact the accuracy and quality of EMIR analysis.\nPerform detailed root-cause analysis of EMIR violations and provide actionable recommendations to Physical Design and other related teams.\nWork closely with Physical Design teams to drive power-grid optimization, via enhancement, metal strengthening, floorplan updates, placement optimization, and ECO-based fixes.\nAnalyze EMIR challenges associated with voltage islands, multiple power domains, power-domain boundaries, bump distribution, and power-grid connectivity.\nIdentify critical issues early in the design cycle that may require floorplan, bump, or power-grid architecture changes.\nAnalyze results across multiple design iterations to identify new violations, regressions, and unexpected changes, and drive them toward resolution.\nWork closely with design teams to determine whether identified EMIR issues can be addressed through ECO changes or require more significant power-grid/design modifications.\nDrive assigned blocks/subsystems toward EMIR signoff and design convergence, while meeting project quality and schedule requirements.\nDevelop and improve automation for EMIR flow execution, data processing, analysis, debug, and reporting.\nCollaborate effectively with cross-functional teams and provide technical guidance and support on EMIR related issues.\nContribute to continuous improvement of EMIR methodologies, checks, best practices, and design closure processes.\nPREFERRED EXPERIENCE:\n4 +Years of hands-on experience in ASIC/SoC Physical Design with significant experience in EMIR analysis and signoff.\nStrong hands-on experience with Ansys RedHawk-SC and/or Cadence Voltus for Electromigration and IR-drop analysis. Experience with both tools is highly preferred.\nStrong understanding of Power Delivery Networks (PDN), static IR drop, dynamic IR drop, Electromigration, current density, and power-grid reliability.\nExperience with EMIR flow setup, database validation, debug, analysis, and signoff closure.\nStrong understanding of the impact of floorplan, placement, routing, power-grid design, vias, and bumps on EMIR.\nExperience in debugging EMIR violations and providing effective and practical design recommendations for issue resolution.\nGood understanding of multi-voltage designs, voltage islands, and power-domain interactions.\nExperience in power-grid robustness analysis and validation and identifying potential design weaknesses early in the implementation cycle.\nFamiliarity with physical design inputs and data such as LEF/DEF, parasi...","description_format":"text","description_chars":13924,"description_truncated":true,"requirements":{"experience_years_min":4,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Computer Components","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-10-20T09:28:01Z"}],"visa":[],"liveness":{"score":31,"band":"fade","label":"Fading","p_open":1,"p_active":0.573,"p_room":0.55,"age_days":16,"expected_fill_days":15,"reasons":["conf:1","stale_co","wave","velocity","win:tail","comp:brand"],"computed_at":"2026-10-22T06:10:10Z"},"pay":null,"html_url":"https://alion.io/job/amd-physical-design-engineer","json_url":"https://alion.io/job/amd-physical-design-engineer.json","meta":{"generated_at":"2026-10-23T01:06:08Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":1855,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-24T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":93},"rest":"https://alion.io/mcp/rest/get_company?id=93"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Famd-physical-design-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Famd-physical-design-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Famd-physical-design-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/amd-physical-design-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Famd-physical-design-engineer"}]}