{"id":3016364,"url":"https://alion.io/job/amd-pll-design-integration-sr-staff-engineer","title":"PLL Design/ Integration Sr Staff Engineer","company":{"id":93,"name":"AMD","domain":"amd.com","url":"https://alion.io/company/amd","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Jibe","truth_index":{"grade":"B","score":80,"open_postings":160,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":20,"computed_at":"2026-10-23T05:54:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["San Jose, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":169000,"max_usd":308000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":527},"experience_years_min":null,"visa_sponsorship":true,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Xilinx Vivado","optional":false},{"name":"SystemVerilog","optional":true}],"status":"live","first_seen_at":"2026-10-21T15:09:00Z","employer_posted_date":"2026-10-21","last_verified_at":"2026-10-23T08:30:41Z","board_verified":true,"closed_at":null,"days_open":1,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":1},"description":"ADVANCE YOUR CAREER. ADVANCE THE WORLD.\nAt AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.\nWhether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Join us and, together, we’ll advance your career.\nTHE ROLE:\nWe are seeking a highly motivated and experienced Staff Design Engineer to join our AECG Fabric team. In this role, you will lead and contribute to the design, integration, and characterization of Phase-Locked Loops (PLLs) for FPGA products across cutting-edge process nodes.\nAs an integral part of AMD's Programmable Logic Group, our global Clock/PLL team is responsible for implementing programmable clocking solutions and methodologies across AMD's expanding portfolio of Adaptive Embedded Computing products. Each new Adaptive SoC introduces a fresh set of programmable clock challenges, driven by evolving system and functional architectures, as well as the adoption of new semiconductor and packaging technologies. Our team collaborates closely with functional architecture, programmable fabric, integration, and software teams to design and deliver innovative clocking solutions - spanning new architectures, clock IPs, tools, and flows.\nThis position offers the opportunity to join a team of industry experts, where you will invent and implement original solutions to complex clocking challenges in some of the largest and most sophisticated SoCs in the industry.\nTHE PERSON:\nYou bring a solid foundation in IC design and manufacturing, including experience with analog/digital IP integration (e.g., PLLs, LDOs, Phase Interpolators), chip design, silicon processes, and packaging technologies. A strong understanding of device physics, reliability, and silicon chip manufacturing is essential.\nYou have a passion for modern adaptive computing architectures and post-silicon validation and characterization. You thrive in collaborative environments, communicate effectively across teams, and bring strong analytical and problem-solving skills to every challenge. You are eager to learn, ready to take initiative, and excited by emerging technologies and innovation.\nKEY RESPONSIBILITIES:\nArchitect and integrate analog/mixed-signal PLL building blocks (VCOs, charge pumps, dividers, PFDs, Loop Filters), LDO, Phase Interpolator, High Speed Divider in to FPGA products across cutting-edge process nodes.\nLead the integration of different PLL topologies (e.g., integer-N, fractional-N, all-digital/ADPLL) to meet specifications for power, area, jitter, and frequency range at product level.\nAddress challenges in advanced node technologies, such as self-heating, electromigration, voltage-controlled oscillator (VCO) linearization and device-level noise optimization for Product level Jitter optimization\nSupervise and verify layouts produced by PD engineers to ensure floor planning, matching, and parasitic minimization using advanced node technologies\nBe responsible for PLL bring up in the lab, conducting performance characterization using state-of-the-art lab equipment\nConduct comprehensive system-level simulations and validation for PLL IP integration in FPGA environment using Vivado or similar tools/flows.\nPREFERRED EXPERIENCE:\nExperience designing fractional-N PLLs, All-Digital PLLs (ADPLL) and/or sub-sampling PLLs is a plus\nFamiliarity with fundamental analog building blocks such as LDOs, bias generators, and operational amplifiers\nBackground in digital design, digital verification, and SystemVerilog modeling\nKnowledge of clock synthesis and recovery techniques, including PLLs, DLLs, and CDRs\nACADEMIC CREDENTIALS:\nPreferably holds an advanced degree (MS) in electrical & electronics engineering; alternatively, a bachelor’s degree with several years of relevant industry experience is acceptable. \nThis role is not eligible for visa sponsorship.\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.\nTHE ROLE:\nWe are seeking a highly motivated and experienced Staff Design Engineer to join our AECG Fabric team. In this role, you will lead and contribute to the design, integration, and characterization of Phase-Locked Loops (PLLs) for FPGA products across cutting-edge process nodes.\nAs an integral part of AMD's Programmable Logic Group, our global Clock/PLL team is responsible for implementing programmable clocking solutions and methodologies across AMD's expanding portfolio of Adaptive Embedded Computing products. Each new Adaptive SoC introduces a fresh set of programmable clock challenges, driven by evolving system and functional architectures, as well as the adoption of new semiconductor and packaging technologies. Our team collaborates closely with functional architecture, programmable fabric, integration, and software teams to design and deliver innovative clocking solutions - spanning new architectures, clock IPs, tools, and flows.\nThis position offers the opportunity to join a team of industry experts, where you will invent and implement original solutions to complex clocking challenges in some of the largest and most sophisticated SoCs in the industry.\nTHE PERSON:\nYou bring a solid foundation in IC design and manufacturing, including experience with analog/digital IP integration (e.g., PLLs, LDOs, Phase Interpolators), chip design, silicon processes, and packaging technologies. A strong understanding of device physics, reliability, and silicon chip manufacturing is essential.\nYou have a passion for modern adaptive computing architectures and post-silicon validation and characterization. You thrive in collaborative environments, communicate effectively across teams, and bring strong analytical and problem-solving skills to every challenge. You are eager to learn, ready to take initiative, and excited by emerging technologies and innovation.\nKEY RESPONSIBILITIES:\nArchitect and integrate analog/mixed-signal PLL building blocks (VCOs, charge pumps, dividers, PFDs, Loop Filters), LDO, Phase Interpolator, High Speed Divider in to FPGA products across cutting-edge process nodes.\nLead the integration of different PLL topologies (e.g., integer-N, fractional-N, all-digital/ADPLL) to meet specifications for power, area, jitter, and frequency range at product level.\nAddress challenges in advanced node technologies, such as self-heating, electromigration, voltage-controlled oscillator (VCO) linearization and device-level noise optimization for Product level Jitter optimization\nSupervise and verify layouts produced by PD engineers to ensure floor planning, matching, and parasitic minimization using advanced node technologies\nBe responsible for PLL bring up in the lab, conducting performance characterization using state-of-the-art lab equipment\nConduct comprehensive system-level simulations and validation for PLL IP integration in FPGA environment using Vivado or similar tools/flows.\nPREFERRED EXPERIENCE:\nExperience designing fractional-N PLLs, All-Digital PLLs (ADPLL) and/or sub-sampling PLLs is a plus\nFamiliarity with fundamental analog building blocks such as LDOs, bias generators, and operational amplifiers\nBackground in digital design, digital verification, and SystemVerilog modeling\nKnowledge of clock synthesis and recovery techniques, including PLLs, DLLs, and CDRs\nACADEMIC CREDENTIALS:\nPreferably holds an advanced degree (MS) in electrical & electronics engineering; alternatively, a bachelor’s degree with several years of relevant industry experience is acceptable. \nThis role is not eligible for visa sponsorship.\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.","description_format":"text","description_chars":9626,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":true},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Computer Components","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-10-21T16:38:26Z"}],"visa":[],"liveness":{"score":63,"band":"ok","label":"Likely open","p_open":1,"p_active":0.632,"p_room":1,"age_days":1,"expected_fill_days":20,"reasons":["conf:1","stale_co","velocity","win:early","comp:brand"],"computed_at":"2026-10-23T05:54:15Z"},"pay":null,"html_url":"https://alion.io/job/amd-pll-design-integration-sr-staff-engineer","json_url":"https://alion.io/job/amd-pll-design-integration-sr-staff-engineer.json","meta":{"generated_at":"2026-10-23T11:30:34Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":17426,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-24T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":93},"rest":"https://alion.io/mcp/rest/get_company?id=93"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Famd-pll-design-integration-sr-staff-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Famd-pll-design-integration-sr-staff-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Famd-pll-design-integration-sr-staff-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/amd-pll-design-integration-sr-staff-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Famd-pll-design-integration-sr-staff-engineer"}]}