{"id":2910201,"url":"https://alion.io/job/amd-power-methodology-and-modelling-engineer","title":"Power Methodology and Modelling Engineer","company":{"id":93,"name":"AMD","domain":"amd.com","url":"https://alion.io/company/amd","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Jibe","truth_index":{"grade":"A","score":97,"open_postings":17,"ghost_share":0,"stale_share":0.118,"repost_share":0,"time_to_fill_p50_days":49,"computed_at":"2026-11-06T05:58:05Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":null,"employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Santa Clara, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":86000,"max_usd":201000,"period":"year","method":"role_country_seniority_unknown","sample_n":15150},"experience_years_min":null,"visa_sponsorship":true,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Python","optional":true}],"status":"closed","first_seen_at":"2026-10-07T13:54:00Z","employer_posted_date":"2026-11-04","last_verified_at":"2026-11-05T09:32:48Z","board_verified":false,"closed_at":"2026-11-05T09:32:48Z","days_open":28,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":28},"description":"ADVANCE YOUR CAREER. ADVANCE THE WORLD.\nAt AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.\nWhether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Join us and, together, we’ll advance your career.\nTHE ROLE\nThe focus of this role is to drive SoC power efficiency methodology with a primary focus on RTL and architecture. The engineer will support the development of IP and SoC power models, analyze power-performance tradeoffs, and identify opportunities to improve power efficiency across AMD products.\nTHE PERSON\nYou have a passion for modern processor architecture, digital design, and verification. You are a collaborative team player with strong communication skills and experience working across global teams and time zones. You possess excellent analytical and problem-solving abilities, a passion for learning, and the initiative to tackle complex technical challenges.\nKEY RESPONSIBILITIES\nContribute to SoC power methodology, RTL power analysis, and optimization to improve power efficiency across the SoC.\nCollaborate with architecture, RTL design, verification, and power teams to identify, evaluate, and implement power-efficiency features and enhancements.\nAnalyze power and performance tradeoffs using power models, RTL simulations, workloads, and design data to support product power targets.\nEvaluate simulation and emulation traces for power projection and correlate projections with power-model predictions and silicon data when available.\nSupport the development and continuous improvement of SoC power models and methodologies, with opportunities to grow ownership of power-modeling activities.\nAnalyze power results, identify key power contributors and anomalies, and work with design teams to drive RTL power optimizations.\nDrive power-efficiency ideas from concept through RTL implementation, validation, and measurable power improvements.\nApply power methodology and analysis techniques to identify and implement RTL and SoC-level power-efficiency enhancements.\nPREFERRED EXPERIENCE\nStrong foundation in RTL design, digital logic, and SoC architecture, with exposure to CPU, memory subsystems, fabrics, I/O, clocking, or power-management features.\nExperience with, or strong interest in, RTL power analysis, low-power design techniques, power methodology, and power-efficiency optimization.\nUnderstanding of power-management concepts and how architecture and RTL design decisions impact SoC power and performance.\nExposure to power modeling, power projection, and model-based power analysis methodologies.\nExperience with hardware emulation and the use of emulation traces for power projection and analysis is a plus.\nInterest in learning and growing expertise in SoC power modeling, methodology development, power projection, validation, and correlation.\nStrong analytical and problem-solving skills with the ability to identify and drive power-efficiency opportunities across engineering disciplines.\nProgramming and scripting experience, with Python preferred.\nACADEMIC CREDENTIALS\nBachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.\nLOCATION\nSanta Clara, CA\nThis role is not eligible for visa sponsorship.\n\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.\nTHE ROLE\nThe focus of this role is to drive SoC power efficiency methodology with a primary focus on RTL and architecture. The engineer will support the development of IP and SoC power models, analyze power-performance tradeoffs, and identify opportunities to improve power efficiency across AMD products.\nTHE PERSON\nYou have a passion for modern processor architecture, digital design, and verification. You are a collaborative team player with strong communication skills and experience working across global teams and time zones. You possess excellent analytical and problem-solving abilities, a passion for learning, and the initiative to tackle complex technical challenges.\nKEY RESPONSIBILITIES\nContribute to SoC power methodology, RTL power analysis, and optimization to improve power efficiency across the SoC.\nCollaborate with architecture, RTL design, verification, and power teams to identify, evaluate, and implement power-efficiency features and enhancements.\nAnalyze power and performance tradeoffs using power models, RTL simulations, workloads, and design data to support product power targets.\nEvaluate simulation and emulation traces for power projection and correlate projections with power-model predictions and silicon data when available.\nSupport the development and continuous improvement of SoC power models and methodologies, with opportunities to grow ownership of power-modeling activities.\nAnalyze power results, identify key power contributors and anomalies, and work with design teams to drive RTL power optimizations.\nDrive power-efficiency ideas from concept through RTL implementation, validation, and measurable power improvements.\nApply power methodology and analysis techniques to identify and implement RTL and SoC-level power-efficiency enhancements.\nPREFERRED EXPERIENCE\nStrong foundation in RTL design, digital logic, and SoC architecture, with exposure to CPU, memory subsystems, fabrics, I/O, clocking, or power-management features.\nExperience with, or strong interest in, RTL power analysis, low-power design techniques, power methodology, and power-efficiency optimization.\nUnderstanding of power-management concepts and how architecture and RTL design decisions impact SoC power and performance.\nExposure to power modeling, power projection, and model-based power analysis methodologies.\nExperience with hardware emulation and the use of emulation traces for power projection and analysis is a plus.\nInterest in learning and growing expertise in SoC power modeling, methodology development, power projection, validation, and correlation.\nStrong analytical and problem-solving skills with the ability to identify and drive power-efficiency opportunities across engineering disciplines.\nProgramming and scripting experience, with Python preferred.\nACADEMIC CREDENTIALS\nBachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.\nLOCATION\nSanta Clara, CA\nThis role is not eligible for visa sponsorship.\n\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.","description_format":"text","description_chars":8466,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Computer Components","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-10-20T09:19:33Z"},{"event":"close","at":"2026-11-04T01:47:01Z"},{"event":"reopen","at":"2026-11-04T06:45:42Z"},{"event":"close","at":"2026-11-05T09:32:48Z"}],"visa":[],"liveness":null,"pay":null,"html_url":"https://alion.io/job/amd-power-methodology-and-modelling-engineer","json_url":"https://alion.io/job/amd-power-methodology-and-modelling-engineer.json","meta":{"generated_at":"2026-11-06T11:32:13Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":20959,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-07T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":93},"rest":"https://alion.io/mcp/rest/get_company?id=93"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Famd-power-methodology-and-modelling-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Famd-power-methodology-and-modelling-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Famd-power-methodology-and-modelling-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/amd-power-methodology-and-modelling-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Famd-power-methodology-and-modelling-engineer"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":2910201}},{"tool":"search_jobs","arguments":{"company":"amd.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":2910201},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. Docs: https://alion.io/developers"}}