{"id":2912069,"url":"https://alion.io/job/amd-principal-cache-rtl-design-cpu-team","title":"Principal Cache RTL Design - CPU Team","company":{"id":93,"name":"AMD","domain":"amd.com","url":"https://alion.io/company/amd","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Jibe","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":28000,"max_usd":64000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":741},"experience_years_min":15,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":true},{"name":"Python","optional":true},{"name":"Verilog","optional":true}],"status":"live","first_seen_at":"2026-06-17T11:58:00Z","employer_posted_date":"2026-10-20","last_verified_at":"2026-10-20T22:16:51Z","board_verified":true,"closed_at":null,"days_open":125,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":125},"description":"WHAT YOU DO AT AMD CHANGES EVERYTHING\nAt AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gamingand embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuityand a shared passion to create something extraordinary. When you join AMD, you’lldiscover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.Together, we advance your career.\nPMTS SILICON DESIGN ENGINEER\nTHE PERSON:\nYou have a passion for modern, complex processor architecture, digital design as well as verification/design quality. You are a team player who has excellent communication skills, strong analytical & problem-solving skills and are willing to learn and ready to take on problems. A global mindset and ability to work in a multi - site environment are keys to being successful in this role.\nKEY RESPONSIBILITIES:\nRTL design of high performance x86-core ISA features, clock/reset/power features of processor, IP Integration, sub-system level design\nArchitect and design of power management features, cache, coherency.\nDesign optimization for implementing power efficient IP, implementing the RTL using low power techniques\nResponsible for the inter IP integration issues resolution\nOwn the Clock-Domain crossing, Linting aspects of the overall design of the IP and the subsystem.\nWork closely with DFT, Physical Design and SOC teams to incorporate the interdisciplinary feedback into the design\nArchitecting, micro-architecting and documentation of the design features\nLead design team from all aspects of the RTL deliverables.\nMentor the junior members of the RTL team to meet the team goals\nRepresents AMD to the outside technical community, partners and vendors\nYour commitment to innovating as a team demonstrated through excellent communication, knowledge of proper documentation techniques, and independently driving tasks to completion.\nPREFERRED EXPERIENCE:\n15+ years of experience in Digital IP/ASIC design and Verilog RTL development\nExperience in full IP design cycle, requirements definition, architecture and microarchitecture specification.\nShould be well versed with RTL design verification, design quality checks, synthesis, timing closure and post silicon validation.\nExpert on Verilog RTL design and has experience of multiscale digital IP/ASIC projects.\nShould possess expertise in front-end EDA tools sign-off and its flows.\nFamiliarity with low power design and low power flow is an added plus.\nAbility to program with scripting languages such as Python or Perl is a plus;\nHighly motivated to seek out solutions and willing to learn new skills to fulfill job requirements;\nProven interpersonal skills, leadership and teamwork;\nExcellent writing skills in the English language, editing and organizational skills required;\nSkilled at prioritization and multi-tasking;\nGood understanding of engineering terminology used within the semiconductor industry;\nGood understanding of digital design concepts;\nKnowledge of, or experience in, functional design verification or design is highly desired.\nACADEMIC CREDENTIALS:\nMaster’s degree preferred with emphasis in Electrical/Electronics Engineering, Computer Engineering, or VLSI design Engineering.\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.\nPMTS SILICON DESIGN ENGINEER\nTHE PERSON:\nYou have a passion for modern, complex processor architecture, digital design as well as verification/design quality. You are a team player who has excellent communication skills, strong analytical & problem-solving skills and are willing to learn and ready to take on problems. A global mindset and ability to work in a multi - site environment are keys to being successful in this role.\nKEY RESPONSIBILITIES:\nRTL design of high performance x86-core ISA features, clock/reset/power features of processor, IP Integration, sub-system level design\nArchitect and design of power management features, cache, coherency.\nDesign optimization for implementing power efficient IP, implementing the RTL using low power techniques\nResponsible for the inter IP integration issues resolution\nOwn the Clock-Domain crossing, Linting aspects of the overall design of the IP and the subsystem.\nWork closely with DFT, Physical Design and SOC teams to incorporate the interdisciplinary feedback into the design\nArchitecting, micro-architecting and documentation of the design features\nLead design team from all aspects of the RTL deliverables.\nMentor the junior members of the RTL team to meet the team goals\nRepresents AMD to the outside technical community, partners and vendors\nYour commitment to innovating as a team demonstrated through excellent communication, knowledge of proper documentation techniques, and independently driving tasks to completion.\nPREFERRED EXPERIENCE:\n15+ years of experience in Digital IP/ASIC design and Verilog RTL development\nExperience in full IP design cycle, requirements definition, architecture and microarchitecture specification.\nShould be well versed with RTL design verification, design quality checks, synthesis, timing closure and post silicon validation.\nExpert on Verilog RTL design and has experience of multiscale digital IP/ASIC projects.\nShould possess expertise in front-end EDA tools sign-off and its flows.\nFamiliarity with low power design and low power flow is an added plus.\nAbility to program with scripting languages such as Python or Perl is a plus;\nHighly motivated to seek out solutions and willing to learn new skills to fulfill job requirements;\nProven interpersonal skills, leadership and teamwork;\nExcellent writing skills in the English language, editing and organizational skills required;\nSkilled at prioritization and multi-tasking;\nGood understanding of engineering terminology used within the semiconductor industry;\nGood understanding of digital design concepts;\nKnowledge of, or experience in, functional design verification or design is highly desired.\nACADEMIC CREDENTIALS:\nMaster’s degree preferred with emphasis in Electrical/Electronics Engineering, Computer Engineering, or VLSI design Engineering.\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.","description_format":"text","description_chars":8243,"description_truncated":false,"requirements":{"experience_years_min":15,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"master","optional":true},"security_clearance":false,"languages":[{"language":"English","level":"All levels","optional":false}]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Computer Components","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-10-20T09:44:57Z"}],"visa":[],"liveness":{"score":7,"band":"cold","label":"Long shot","p_open":1,"p_active":0.251,"p_room":0.28,"age_days":125,"expected_fill_days":14,"reasons":["conf:2","win:tail","crowd:brand"],"computed_at":"2026-10-21T00:40:24Z"},"pay":null,"html_url":"https://alion.io/job/amd-principal-cache-rtl-design-cpu-team","json_url":"https://alion.io/job/amd-principal-cache-rtl-design-cpu-team.json","meta":{"generated_at":"2026-10-21T00:40:24Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":1016,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-22T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":93},"rest":"https://alion.io/mcp/rest/get_company?id=93"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Famd-principal-cache-rtl-design-cpu-team"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Famd-principal-cache-rtl-design-cpu-team"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Famd-principal-cache-rtl-design-cpu-team"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/amd-principal-cache-rtl-design-cpu-team\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Famd-principal-cache-rtl-design-cpu-team"}]}