{"id":3183759,"url":"https://alion.io/job/amd-rtl-design-engineer-8","title":"RTL Design Engineer","company":{"id":93,"name":"AMD","domain":"amd.com","url":"https://alion.io/company/amd","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Jibe","truth_index":{"grade":"B","score":75,"open_postings":162,"ghost_share":0,"stale_share":0.994,"repost_share":0,"time_to_fill_p50_days":29,"computed_at":"2026-10-25T05:49:26Z"}},"role":"Hardware","role_family":"Hardware","seniority":null,"employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Markham, Canada"],"countries":["CA"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":65000,"max_usd":130000,"period":"year","method":"role_country_seniority_unknown","sample_n":146},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":true},{"name":"Python","optional":true},{"name":"Ruby","optional":true},{"name":"SystemVerilog","optional":true},{"name":"Verilog","optional":true}],"status":"live","first_seen_at":"2026-10-23T18:57:00Z","employer_posted_date":"2026-10-23","last_verified_at":"2026-10-25T17:12:45Z","board_verified":true,"closed_at":null,"days_open":1,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":1},"description":"ADVANCE YOUR CAREER. ADVANCE THE WORLD.\nAt AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.\nWhether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Join us and, together, we’ll advance your career.\n THE ROLE:\nWe are seeking a highly motivated RTL IP Design Engineer to join AMD's Security IP (SECIP) Design team. The team is responsible for the architecture, design, and verification of a broad range of embedded microprocessor (MP) subsystems and hardware accelerators that are critical to enhancing performance, functionality, security, and efficiency across AMD System-on-Chip (SoC) products spanning client, server, graphics, and gaming platforms.\nIn this role, you will contribute to block-level RTL design and subsystem-level integration for complex embedded MP subsystems. Your work will directly influence technologies including security policy management, cryptography, data compression, high-throughput DMA, power management, and other advanced subsystem applications.\nYou will collaborate closely with the IP Architecture team to define functional specifications, establish and track design objectives, and drive RTL development through implementation and optimization. Working alongside experienced design engineers, you will help deliver high-quality solutions that meet performance, power, and area (PPA) targets while maintaining robust design quality and scalability.\nTHE PERSON:\nYou are a talented and results-oriented RTL design engineer with a strong track record of technical ownership and execution. You are passionate about developing high-quality hardware designs and driving complex IP and subsystem projects from concept through completion.\nYou proactively identify opportunities to improve methodologies and workflows, anticipate and resolve technical challenges, and thrive in a fast-paced, collaborative environment. You possess strong analytical and problem-solving skills, exceptional attention to detail, and excellent written and verbal communication abilities. You are also committed to supporting team success through collaboration, knowledge sharing, and mentorship.\nKEY RESPONSIBILITIES:\nDevelop and maintain block-level RTL IP and MP subsystem specifications, microarchitecture, RTL implementations, and associated design methodologies and infrastructure.\nDesign, implement, and debug RTL solutions using AI-powered methodologies, directed C-DPI based testing, and verification team testbenches and regression environments, to achieve functional and coverage closure.\nAnalyze regression failures, debug simulations, evaluate coverage results, and collaborate with design, verification, and implementation teams to achieve functional and design-quality closure, including lint, timing, DFT, DFP, and other signoff requirements.\nContribute to verification planning by reviewing feature specifications, defining test plans, influencing testbench architecture, and promoting design-for-verification best practices.\nDebug and resolve subsystem and SoC integration issues in collaboration with SoC Integration, SoC Design Verification, emulation, and post-silicon validation teams.\nProvide technical leadership in IP architecture, RTL design methodologies, and critical problem resolution, commensurate with experience level.\nPREFERRED EXPERIENCE:\nStrong understanding of CPU and embedded microprocessor subsystem architectures, datapath-oriented accelerator microarchitectures, and FPGA-based emulation and prototyping methodologies.\nProficiency in Verilog and SystemVerilog, along with scripting languages such as Python, Tcl, Perl, Ruby, and Make.\nSolid knowledge of both traditional and AI-powered RTL design and verification methodologies, industry best practices, and C-DPI based verification techniques.\nStrong understanding of industry-standard bus and interface protocols, including AXI, AHB, and AMBA.\nExperience with ASIC development tools and flows, including simulation, debug, linting, synthesis, timing analysis, and power-aware verification.\nDomain-specific expertise in security, processor subsystems, accelerators, or related areas, along with demonstrated technical leadership capabilities for senior-level candidates.\nACADEMIC CREDENTIALS:\nBachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline.\nMaster's degree preferred.\nLOCATION:\nMarkham, Ontario\nAustin, Texas\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.\nTHE ROLE:\nWe are seeking a highly motivated RTL IP Design Engineer to join AMD's Security IP (SECIP) Design team. The team is responsible for the architecture, design, and verification of a broad range of embedded microprocessor (MP) subsystems and hardware accelerators that are critical to enhancing performance, functionality, security, and efficiency across AMD System-on-Chip (SoC) products spanning client, server, graphics, and gaming platforms.\nIn this role, you will contribute to block-level RTL design and subsystem-level integration for complex embedded MP subsystems. Your work will directly influence technologies including security policy management, cryptography, data compression, high-throughput DMA, power management, and other advanced subsystem applications.\nYou will collaborate closely with the IP Architecture team to define functional specifications, establish and track design objectives, and drive RTL development through implementation and optimization. Working alongside experienced design engineers, you will help deliver high-quality solutions that meet performance, power, and area (PPA) targets while maintaining robust design quality and scalability.\nTHE PERSON:\nYou are a talented and results-oriented RTL design engineer with a strong track record of technical ownership and execution. You are passionate about developing high-quality hardware designs and driving complex IP and subsystem projects from concept through completion.\nYou proactively identify opportunities to improve methodologies and workflows, anticipate and resolve technical challenges, and thrive in a fast-paced, collaborative environment. You possess strong analytical and problem-solving skills, exceptional attention to detail, and excellent written and verbal communication abilities. You are also committed to supporting team success through collaboration, knowledge sharing, and mentorship.\nKEY RESPONSIBILITIES:\nDevelop and maintain block-level RTL IP and MP subsystem specifications, microarchitecture, RTL implementations, and associated design methodologies and infrastructure.\nDesign, implement, and debug RTL solutions using AI-powered methodologies, directed C-DPI based testing, and verification team testbenches and regression environments, to achieve functional and coverage closure.\nAnalyze regression failures, debug simulations, evaluate coverage results, and collaborate with design, verification, and implementation teams to achieve functional and design-quality closure, including lint, timing, DFT, DFP, and other signoff requirements.\nContribute to verification planning by reviewing feature specifications, defining test plans, influencing testbench architecture, and promoting design-for-verification best practices.\nDebug and resolve subsystem and SoC integration issues in collaboration with SoC Integration, SoC Design Verification, emulation, and post-silicon validation teams.\nProvide technical leadership in IP architecture, RTL design methodologies, and critical problem resolution, commensurate with experience level.\nPREFERRED EXPERIENCE:\nStrong understanding of CPU and embedded microprocessor subsystem architectures, datapath-oriented accelerator microarchitectures, and FPGA-based emulation and prototyping methodologies.\nProficiency in Verilog and SystemVerilog, along with scripting languages such as Python, Tcl, Perl, Ruby, and Make.\nSolid knowledge of both traditional and AI-powered RTL design and verification methodologies, industry best practices, and C-DPI based verification techniques.\nStrong understanding of industry-standard bus and interface protocols, including AXI, AHB, and AMBA.\nExperience with ASIC development tools and flows, including simulation, debug, linting, synthesis, timing analysis, and power-aware verification.\nDomain-specific expertise in security, processor subsystems, accelerators, or related areas, along with demonstrated technical leadership capabilities for senior-level candidates.\nACADEMIC CREDENTIALS:\nBachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline.\nMaster's degree preferred.\nLOCATION:\nMarkham, Ontario\nAustin, Texas\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.","description_format":"text","description_chars":10845,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":true},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Computer Components","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-10-23T22:32:24Z"}],"visa":[],"liveness":{"score":70,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.695,"p_room":1,"age_days":1,"expected_fill_days":29,"reasons":["conf:0","stale_co","wave","velocity","win:early","comp:brand"],"computed_at":"2026-10-25T05:49:26Z"},"pay":null,"html_url":"https://alion.io/job/amd-rtl-design-engineer-8","json_url":"https://alion.io/job/amd-rtl-design-engineer-8.json","meta":{"generated_at":"2026-10-25T17:49:49Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":25488,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-26T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":93},"rest":"https://alion.io/mcp/rest/get_company?id=93"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Famd-rtl-design-engineer-8"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Famd-rtl-design-engineer-8"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Famd-rtl-design-engineer-8"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/amd-rtl-design-engineer-8\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Famd-rtl-design-engineer-8"}]}