{"id":3066119,"url":"https://alion.io/job/amd-senior-analog-layout-engineer","title":"Senior Analog layout Engineer","company":{"id":93,"name":"AMD","domain":"amd.com","url":"https://alion.io/company/amd","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Jibe","truth_index":{"grade":"B","score":80,"open_postings":160,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":20,"computed_at":"2026-10-23T05:54:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hyderabad, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":17500,"max_usd":45000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":18},"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Virtuoso","optional":true}],"status":"live","first_seen_at":"2026-10-22T06:06:00Z","employer_posted_date":"2026-10-22","last_verified_at":"2026-10-23T18:20:04Z","board_verified":true,"closed_at":null,"days_open":1,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":1},"description":"ADVANCE YOUR CAREER. ADVANCE THE WORLD.\nAt AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.\nWhether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Join us and, together, we’ll advance your career.\nTHE ROLE:\nAMD is looking for a talented individual to join the Design Engineering team as a Staff Analog Layout Design Engineer in advanced process technology node 7nm and below. design high performance analog and digital circuits such as ADCs, DACs, PLLs, HBM, GDDR, DDR, LPDDR, References, Custom IOs, LDO, ESD which are integrated into AMD products\nTHE PERSON:\nAn experienced Analog Layout design engineer should be innovative, collaborative, meticulous, and curious.\nKEY RESPONSIBILITIES:\nStrong foundation in layout design for mixed analog / digital ICs with 7nm and below CMOS process geometries experience\nExperience in the layout of high performance data converters and / or high speed (GHz) circuit design would be an advantage\nExtensive Floorplanning, power grid and signal flow planning experience\nExperience in LVS, DRC, ERC, ANT, ESD, Latch-up, EMIR and Reliability\nExcellent understanding of signal and clock shielding and isolation techniques\nExcellent understanding of process non-idealities such as STI stress, well proximity effect and CMP effects and design strategies to mitigate these effects\nExcellent written and oral communication skills are also required\nAbility to work well as part of a team\nExcellent problem solving skills\nStrong foundation in layout design for mixed analog / digital ICs with 7nm and below CMOS process geometries experience\nExperience in the layout of high performance data converters and / or high speed (GHz) circuit design would be an advantage\nExtensive Floorplanning, power grid and signal flow planning experience\nExperience in LVS, DRC, ERC, ANT, ESD, Latch-up, EMIR and Reliability\nExcellent understanding of signal and clock shielding and isolation techniques\nExcellent understanding of process non-idealities such as STI stress, well proximity effect and CMP effects and design strategies to mitigate these effects\nExcellent written and oral communication skills are also required\nAbility to work well as part of a team\nExcellent problem solving skills\nPREFERRED EXPERIENCE:\nMust have detailed knowledge of CMOS circuit theory.\nMust have ability to communicate with various teams to articulate specs and requirements as they pertain to layout\nLayout design and verification experience using Cadence Virtuoso and Mentor Calibre tools\nMust have at least 8 years of relevant or comparable experience doing analog layout design\nKnowledge of chip level integration and ESD concepts a plus\nExperience in LVS, DRC, ERC, ANT, ESD, Latch-up, EMIR and Reliability\nGood understanding of signal and clock shielding and isolation techniques\nAbility to work well as part of a team\nACADEMIC CREDENTIALS:\nBachelors or Masters degree in Electronics and Communication Engineering with 4+Yrs of exp\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.\nTHE ROLE:\nAMD is looking for a talented individual to join the Design Engineering team as a Staff Analog Layout Design Engineer in advanced process technology node 7nm and below. design high performance analog and digital circuits such as ADCs, DACs, PLLs, HBM, GDDR, DDR, LPDDR, References, Custom IOs, LDO, ESD which are integrated into AMD products\nTHE PERSON:\nAn experienced Analog Layout design engineer should be innovative, collaborative, meticulous, and curious.\nKEY RESPONSIBILITIES:\nStrong foundation in layout design for mixed analog / digital ICs with 7nm and below CMOS process geometries experience\nExperience in the layout of high performance data converters and / or high speed (GHz) circuit design would be an advantage\nExtensive Floorplanning, power grid and signal flow planning experience\nExperience in LVS, DRC, ERC, ANT, ESD, Latch-up, EMIR and Reliability\nExcellent understanding of signal and clock shielding and isolation techniques\nExcellent understanding of process non-idealities such as STI stress, well proximity effect and CMP effects and design strategies to mitigate these effects\nExcellent written and oral communication skills are also required\nAbility to work well as part of a team\nExcellent problem solving skills\nStrong foundation in layout design for mixed analog / digital ICs with 7nm and below CMOS process geometries experience\nExperience in the layout of high performance data converters and / or high speed (GHz) circuit design would be an advantage\nExtensive Floorplanning, power grid and signal flow planning experience\nExperience in LVS, DRC, ERC, ANT, ESD, Latch-up, EMIR and Reliability\nExcellent understanding of signal and clock shielding and isolation techniques\nExcellent understanding of process non-idealities such as STI stress, well proximity effect and CMP effects and design strategies to mitigate these effects\nExcellent written and oral communication skills are also required\nAbility to work well as part of a team\nExcellent problem solving skills\nPREFERRED EXPERIENCE:\nMust have detailed knowledge of CMOS circuit theory.\nMust have ability to communicate with various teams to articulate specs and requirements as they pertain to layout\nLayout design and verification experience using Cadence Virtuoso and Mentor Calibre tools\nMust have at least 8 years of relevant or comparable experience doing analog layout design\nKnowledge of chip level integration and ESD concepts a plus\nExperience in LVS, DRC, ERC, ANT, ESD, Latch-up, EMIR and Reliability\nGood understanding of signal and clock shielding and isolation techniques\nAbility to work well as part of a team\nACADEMIC CREDENTIALS:\nBachelors or Masters degree in Electronics and Communication Engineering with 4+Yrs of exp\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.","description_format":"text","description_chars":7936,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Computer Components","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-10-22T08:01:57Z"}],"visa":[],"liveness":{"score":63,"band":"ok","label":"Likely open","p_open":1,"p_active":0.632,"p_room":1,"age_days":0,"expected_fill_days":20,"reasons":["conf:1","stale_co","velocity","win:early","comp:brand"],"computed_at":"2026-10-23T05:54:15Z"},"pay":null,"html_url":"https://alion.io/job/amd-senior-analog-layout-engineer","json_url":"https://alion.io/job/amd-senior-analog-layout-engineer.json","meta":{"generated_at":"2026-10-23T20:43:17Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":2444,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-24T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":93},"rest":"https://alion.io/mcp/rest/get_company?id=93"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Famd-senior-analog-layout-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Famd-senior-analog-layout-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Famd-senior-analog-layout-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/amd-senior-analog-layout-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Famd-senior-analog-layout-engineer"}]}