{"id":2910093,"url":"https://alion.io/job/amd-senior-asic-rtl-design-engineer-ai-networking-ip","title":"Senior ASIC RTL Design Engineer, AI Networking IP","company":{"id":93,"name":"AMD","domain":"amd.com","url":"https://alion.io/company/amd","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Jibe","truth_index":{"grade":"B","score":75,"open_postings":164,"ghost_share":0,"stale_share":0.994,"repost_share":0,"time_to_fill_p50_days":29,"computed_at":"2026-10-27T05:46:45Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Ottawa, Canada"],"countries":["CA"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":82000,"max_usd":144000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":74},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Verilog","optional":false},{"name":"ChatGPT","optional":true},{"name":"Claude","optional":true},{"name":"Copilot","optional":true},{"name":"Cursor","optional":true},{"name":"OpenAI Codex","optional":true},{"name":"Perl","optional":true},{"name":"Python","optional":true},{"name":"SystemVerilog","optional":true}],"status":"live","first_seen_at":"2026-10-09T22:06:00Z","employer_posted_date":"2026-10-20","last_verified_at":"2026-10-27T18:10:31Z","board_verified":true,"closed_at":null,"days_open":17,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":17},"description":"ADVANCE YOUR CAREER. ADVANCE THE WORLD.\nAt AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.\nWhether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Join us and, together, we’ll advance your career.\n THE ROLE:\nWe are looking for a talented ASIC RTL Design Engineer to join our IP design team developing high-performance networking and communications IP for advanced AMD products. Our intellectual property (IP) design team creates IP cores for use in high performance AMD products. Our designers work on industry-leading technologies for AI networking and communications. Your expertise will be deployed in ASIC projects targeting networking, security, storage, and other applications.\nTHE PERSON:\nYou are very proficient in Verilog RTL coding, and front-end design flows. You have experience with ASIC RTL design and front-end design processes, ideally including networking, communications, or other high-speed interface protocols. You have demonstrated your technical skill through prior experience delivering ASIC and/or FPGA solutions to the market, and leverage this experience to design and code innovative, high quality IP products.\nYou are a team player who has excellent written and verbal communication skills with experience collaborating across multiple design sites and time zones. You have strong analytical and problem-solving skills and enjoy tackling new challenges. You are a self-starter with a desire to learn and an ability to solve complex, novel, and non-recurring problems. You pay attention to details. You enjoy working amongst a multi-disciplinary team of professionals with diverse skills and experiences to complete projects in an efficient manner.\nKEY RESPONSIBILITIES:\nDevelop synthesizable RTL for IP cores targeting advanced technology nodes\nUtilize modern AI tools to achieve a high level of RTL design productivity through code generation, refactoring, documentation, and debug\nCollaborate directly with IP Architecture, IP Verification, and SoC integration teams\nContribute to design specifications for IP cores\nResolve IP simulation regression failures through close collaboration with the IP Verification Team and work with Verification Team members to ensure achievement of verification quality metrics\n\nWork with the SoC and Physical Design (PD) teams to meet Power/Performance/Area goals by providing synthesis and timing closure support\n\nSupport the activities of the Emulation Team\nCoach and mentor less experienced designers\nAttend and contribute to regular technical status meetings\nPREFERRED EXPERIENCE:\nRTL (Verilog/SystemVerilog) design experience, preferably including ASIC implementations targeting leading-edge technologies\n\nProven experience with industry-leading ASIC design tools, synthesis tools, flows, and timing closure\nExperience driving AI-powered tools (VS Code, GitHub Copilot, Cursor) that integrate LLMs (Claude, Codex/GPT) for RTL design\nExperience executing design checks such as lint, CDC, and LEC using industry standard ASIC tools\nSkilled in simulation and debugging with functional verification tools from Synopsys, Cadence, and/or Siemens (Mentor) including Gate-level simulations\nExcellent understanding of standard bus/interface protocols (i.e. AXI, AHB, AMBA)\nExperience in modern, complex networking architecture and digital design in general\nExperience with networking or high-speed interface protocols such as Ethernet or PCIe, digital communication systems, or packet-processing applications\nsystems, optical communications, and packet processing applications\nFamiliarity with encryption protocols (such as MACsec and IPsec) and security technologies for digital communication systems\nProficient with workplace AI tools (Microsoft M365 Copilot, ChatGPT, Atlassian Rovo)\nProficient with scripting languages such as Python, Perl, TCL, Makefile, and csh/bash.\nACADEMIC CREDENTIALS:\nBachelors or Mastersdegree in computer engineering/Electrical Engineering\nLOCATION: Ottawa, ON or Markham, ON\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.\nTHE ROLE:\nWe are looking for a talented ASIC RTL Design Engineer to join our IP design team developing high-performance networking and communications IP for advanced AMD products. Our intellectual property (IP) design team creates IP cores for use in high performance AMD products. Our designers work on industry-leading technologies for AI networking and communications. Your expertise will be deployed in ASIC projects targeting networking, security, storage, and other applications.\nTHE PERSON:\nYou are very proficient in Verilog RTL coding, and front-end design flows. You have experience with ASIC RTL design and front-end design processes, ideally including networking, communications, or other high-speed interface protocols. You have demonstrated your technical skill through prior experience delivering ASIC and/or FPGA solutions to the market, and leverage this experience to design and code innovative, high quality IP products.\nYou are a team player who has excellent written and verbal communication skills with experience collaborating across multiple design sites and time zones. You have strong analytical and problem-solving skills and enjoy tackling new challenges. You are a self-starter with a desire to learn and an ability to solve complex, novel, and non-recurring problems. You pay attention to details. You enjoy working amongst a multi-disciplinary team of professionals with diverse skills and experiences to complete projects in an efficient manner.\nKEY RESPONSIBILITIES:\nDevelop synthesizable RTL for IP cores targeting advanced technology nodes\nUtilize modern AI tools to achieve a high level of RTL design productivity through code generation, refactoring, documentation, and debug\nCollaborate directly with IP Architecture, IP Verification, and SoC integration teams\nContribute to design specifications for IP cores\nResolve IP simulation regression failures through close collaboration with the IP Verification Team and work with Verification Team members to ensure achievement of verification quality metrics\n\nWork with the SoC and Physical Design (PD) teams to meet Power/Performance/Area goals by providing synthesis and timing closure support\n\nSupport the activities of the Emulation Team\nCoach and mentor less experienced designers\nAttend and contribute to regular technical status meetings\nPREFERRED EXPERIENCE:\nRTL (Verilog/SystemVerilog) design experience, preferably including ASIC implementations targeting leading-edge technologies\n\nProven experience with industry-leading ASIC design tools, synthesis tools, flows, and timing closure\nExperience driving AI-powered tools (VS Code, GitHub Copilot, Cursor) that integrate LLMs (Claude, Codex/GPT) for RTL design\nExperience executing design checks such as lint, CDC, and LEC using industry standard ASIC tools\nSkilled in simulation and debugging with functional verification tools from Synopsys, Cadence, and/or Siemens (Mentor) including Gate-level simulations\nExcellent understanding of standard bus/interface protocols (i.e. AXI, AHB, AMBA)\nExperience in modern, complex networking architecture and digital design in general\nExperience with networking or high-speed interface protocols such as Ethernet or PCIe, digital communication systems, or packet-processing applications\nsystems, optical communications, and packet processing applications\nFamiliarity with encryption protocols (such as MACsec and IPsec) and security technologies for digital communication systems\nProficient with workplace AI tools (Microsoft M365 Copilot, ChatGPT, Atlassian Rovo)\nProficient with scripting languages such as Python, Perl, TCL, Makefile, and csh/bash.\nACADEMIC CREDENTIALS:\nBachelors or Mastersdegree in computer engineering/Electrical Engineering\nLOCATION: Ottawa, ON or Markham, ON\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.","description_format":"text","description_chars":9995,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Computer Components","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-10-20T09:19:33Z"}],"visa":[],"liveness":{"score":53,"band":"ok","label":"Likely open","p_open":1,"p_active":0.594,"p_room":0.9,"age_days":17,"expected_fill_days":29,"reasons":["conf:1","stale_co","velocity","win:mid","comp:brand"],"computed_at":"2026-10-27T05:46:45Z"},"pay":null,"html_url":"https://alion.io/job/amd-senior-asic-rtl-design-engineer-ai-networking-ip","json_url":"https://alion.io/job/amd-senior-asic-rtl-design-engineer-ai-networking-ip.json","meta":{"generated_at":"2026-10-27T19:17:15Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":9817,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-28T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":93},"rest":"https://alion.io/mcp/rest/get_company?id=93"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Famd-senior-asic-rtl-design-engineer-ai-networking-ip"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Famd-senior-asic-rtl-design-engineer-ai-networking-ip"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Famd-senior-asic-rtl-design-engineer-ai-networking-ip"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/amd-senior-asic-rtl-design-engineer-ai-networking-ip\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Famd-senior-asic-rtl-design-engineer-ai-networking-ip"}]}