{"id":3740208,"url":"https://alion.io/job/amd-senior-cad-and-methodology-design-engineer","title":"Senior CAD And Methodology Design Engineer","company":{"id":93,"name":"AMD","domain":"amd.com","url":"https://alion.io/company/amd","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Jibe","truth_index":{"grade":"A","score":97,"open_postings":17,"ghost_share":0,"stale_share":0.118,"repost_share":0,"time_to_fill_p50_days":49,"computed_at":"2026-11-10T06:52:35Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["George Town, Malaysia"],"countries":["MY"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Python","optional":false},{"name":"Ansys RedHawk","optional":true},{"name":"Ansys Totem","optional":true},{"name":"Synopsys Fusion Compiler","optional":true},{"name":"Synopsys IC Compiler II","optional":true},{"name":"Synopsys PrimeTime","optional":true}],"status":"live","first_seen_at":"2026-11-04T09:17:00Z","employer_posted_date":"2026-11-04","last_verified_at":"2026-11-06T09:08:37Z","board_verified":false,"closed_at":null,"days_open":6,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":6},"description":"ADVANCE YOUR CAREER. ADVANCE THE WORLD.\nAt AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.\nWhether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Join us and, together, we’ll advance your career.\nTHE ROLE\nAs a design engineer in our CAD and methodology team, you will support and optimize the RTL-to-GDS design flow for the Project CAD team in the Adaptive & Embedded Computing Group (AECG). You will work across the complete RTL-to-GDS methodology - synthesis, place-and-route, and physical signoff - support tool deployments, and contribute to flow development across multiple semiconductor projects. You will help enable the tools, PDKs, and collateral the Silicon Development Team needs to operate efficiently, support the unified environment that sets tool, PDK, and design versions for chips in development, work with Silicon development teams requesting newer tool versions, and raise trouble tickets with CAD vendors as needed.\nTHE PERSON\nYou have a passion for modern, complex processor architecture, digital design, and physical implementation. You are a team player with excellent communication skills and experience collaborating with engineers across sites and time zones. You have strong analytical and problem-solving skills, and are eager to learn and take on new challenges.\nKEY RESPONSIBILITIES\nSupport the CAD infrastructure team on the RTL-to-GDS flow across multiple IC design projects\nHelp maintain standardized RTL-to-GDS design flows and methodologies (synthesis → P&R → signoff)\nImplement and support customized RTL-to-GDS flows for Fabric design groups\nWork closely with external tool vendors to help the team meet design and development targets\nDevelop tool-flow methodologies across the digital back-end - synthesis, place-and-route, and sign-off flows for timing, power, EM/IR, and DRC/LVS/DFM\nImprove engineering efficiency while improving design quality in the IP release process\nSupport debug of bugs and issues across the RTL-to-GDS implementation flow\nBuild flows in TCL and Python to ensure quality and faster execution\nLearn methodologies used across the industry to adopt best practices\nLeverage and deploy AMD AI systems to design teams\nPREFERRED EXPERIENCE\nFundamental programming and scripting skills (e.g., TCL, Python, PERL, or similar)\nRTL synthesis and place-and-route flows (Fusion Compiler / IC Compiler / Innovus or equivalent)\nStatic timing analysis and constraints (PrimeTime / SDC)\nPDK and technology enablement\nPhysical signoff: Calibre (DRC/LVS/DFM), extraction, and Totem/Redhawk for EM/IR\nLow-power (UPF) and power-integrity methodology\nStrong written and verbal communication skills\nACADEMIC CREDENTIALS\nBachelor's or Master's degree in Computer Engineering / Electrical Engineering\nLOCATION:\nPenang, Malaysia\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.\nTHE ROLE\nAs a design engineer in our CAD and methodology team, you will support and optimize the RTL-to-GDS design flow for the Project CAD team in the Adaptive & Embedded Computing Group (AECG). You will work across the complete RTL-to-GDS methodology - synthesis, place-and-route, and physical signoff - support tool deployments, and contribute to flow development across multiple semiconductor projects. You will help enable the tools, PDKs, and collateral the Silicon Development Team needs to operate efficiently, support the unified environment that sets tool, PDK, and design versions for chips in development, work with Silicon development teams requesting newer tool versions, and raise trouble tickets with CAD vendors as needed.\nTHE PERSON\nYou have a passion for modern, complex processor architecture, digital design, and physical implementation. You are a team player with excellent communication skills and experience collaborating with engineers across sites and time zones. You have strong analytical and problem-solving skills, and are eager to learn and take on new challenges.\nKEY RESPONSIBILITIES\nSupport the CAD infrastructure team on the RTL-to-GDS flow across multiple IC design projects\nHelp maintain standardized RTL-to-GDS design flows and methodologies (synthesis → P&R → signoff)\nImplement and support customized RTL-to-GDS flows for Fabric design groups\nWork closely with external tool vendors to help the team meet design and development targets\nDevelop tool-flow methodologies across the digital back-end - synthesis, place-and-route, and sign-off flows for timing, power, EM/IR, and DRC/LVS/DFM\nImprove engineering efficiency while improving design quality in the IP release process\nSupport debug of bugs and issues across the RTL-to-GDS implementation flow\nBuild flows in TCL and Python to ensure quality and faster execution\nLearn methodologies used across the industry to adopt best practices\nLeverage and deploy AMD AI systems to design teams\nPREFERRED EXPERIENCE\nFundamental programming and scripting skills (e.g., TCL, Python, PERL, or similar)\nRTL synthesis and place-and-route flows (Fusion Compiler / IC Compiler / Innovus or equivalent)\nStatic timing analysis and constraints (PrimeTime / SDC)\nPDK and technology enablement\nPhysical signoff: Calibre (DRC/LVS/DFM), extraction, and Totem/Redhawk for EM/IR\nLow-power (UPF) and power-integrity methodology\nStrong written and verbal communication skills\nACADEMIC CREDENTIALS\nBachelor's or Master's degree in Computer Engineering / Electrical Engineering\nLOCATION:\nPenang, Malaysia\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.","description_format":"text","description_chars":7598,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[{"name":"Malaysia","iso":"MY","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Computer Components","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-11-04T11:33:59Z"}],"visa":[],"liveness":{"score":81,"band":"hot","label":"Hiring now","p_open":0.9,"p_active":0.903,"p_room":1,"age_days":5,"expected_fill_days":49,"reasons":["conf:93","velocity","win:early","comp:brand"],"computed_at":"2026-11-10T06:52:35Z"},"pay":null,"html_url":"https://alion.io/job/amd-senior-cad-and-methodology-design-engineer","json_url":"https://alion.io/job/amd-senior-cad-and-methodology-design-engineer.json","meta":{"generated_at":"2026-11-10T11:36:17Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":26949,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-11T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.1,"usd":0.01,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":93},"rest":"https://alion.io/mcp/rest/get_company?id=93"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Famd-senior-cad-and-methodology-design-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":2,"usd":0.2},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Famd-senior-cad-and-methodology-design-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.1,"usd":0.01},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Famd-senior-cad-and-methodology-design-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/amd-senior-cad-and-methodology-design-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Famd-senior-cad-and-methodology-design-engineer"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":3740208}},{"tool":"search_jobs","arguments":{"company":"amd.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":3740208},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. Docs: https://alion.io/developers"}}