{"id":2912054,"url":"https://alion.io/job/amd-senior-soc-power-modeling-engineer","title":"Senior SoC Power Modeling Engineer","company":{"id":93,"name":"AMD","domain":"amd.com","url":"https://alion.io/company/amd","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Jibe","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Austin, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":127000,"max_usd":232000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":1396},"experience_years_min":null,"visa_sponsorship":true,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Python","optional":true}],"status":"live","first_seen_at":"2026-06-23T13:54:00Z","employer_posted_date":"2026-10-20","last_verified_at":"2026-10-22T01:24:47Z","board_verified":true,"closed_at":null,"days_open":120,"trust":{"level":"stale","repost_count":0,"flags":["stale"],"days_open":119},"description":"WHAT YOU DO AT AMD CHANGES EVERYTHING\nAt AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gamingand embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuityand a shared passion to create something extraordinary. When you join AMD, you’lldiscover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.Together, we advance your career.\nTHE ROLE:\nWe are seeking a Senior Power Modeling Engineer to drive pre-silicon power modeling and analysis for AMD’s next-generation Embedded x86 SoC platforms. This role plays a critical part in defining use-case-driven power expectations, building SoC-level power models from IP inputs, and enabling informed EDC/TDC, voltage-frequency (VF), and PPA trade-off decisions early in the design cycle.\nTHE PERSON:\nThe ideal candidate brings deep hands-on experience with SoC power modeling methodologies and understands how IP-level power characteristics scale to full-chip behavior. This engineer will collaborate closely with SoC architects, power architects, performance teams, and silicon validation teams to ensure accurate power projections and influence architectural direction.\nKEY RESPONSIBILITIES:\nSoC & Use-Case Power Modeling\nDevelop and maintain SoC-level power models for Embedded x86 platforms using IP-level inputs (CPU, GPU, fabric, memory, and I/O).\n\nCreate use-case-driven power models representing automotive, industrial, edge computing, and customer-specific embedded workloads.\n\nTranslate real-world workloads into model inputs such as activity factors, concurrency, residency, and DVFS states.\n\nPower-Frequency & Electrical Modeling\nBuild and maintain Voltage-Frequency (VF) curves across operating corners.\nDerive and validate EDC / TDC / current limits based on modeled workloads and platform constraints.\nPerform sensitivity studies across frequency, voltage, workload mix, and power states.\nIP-to-SoC Model Integration\nIntegrate IP-level power models into cohesive SoC-level frameworks.\nEnsure consistency of assumptions across IPs (clocking, power states, gating, DVFS).\nIdentify gaps, inconsistencies, or inaccuracies in IP models and drive closure with IP teams.\nArchitecture & Trade-off Analysis\nPartner with SoC and power architects to influence early architectural decisions.\nEvaluate power/performance/area trade-offs for new features, configurations, and SKUs.\nSupport bounding-box analysis and product positioning decisions.\nCorrelation & Continuous Improvement\nSupport pre-silicon to post-silicon correlation of power models.\nRefine models using silicon data, profiling, and validation feedback.\nImprove modeling methodologies, accuracy targets, and documentation.\nPREFERRED EXPERIENCE:\nProfessional experience in power modeling, power estimation, or SoC power analysis\n\nStrong understanding of:\nSoC power architecture and DVFS\nStatic vs dynamic power components\nEDC / TDC / electrical and thermal constraints\nHands-on experience building SoC-level power models from IP-level models\nExperience creating and analyzing VF curves\nExperience with Embedded or Automotive SoCs\nFamiliarity with x86 CPU, GPU, memory, and fabric power behaviors\nExposure to power modeling tools, spreadsheets, or internal frameworks used for pre-silicon estimation\nExperience with workload-driven modeling and benchmark abstraction\nStrong analytical and scripting skills (Python preferred)\nAbility to work across architecture, IP, performance, and validation teams\nPrior involvement in power correlation with silicon\nAbility to clearly communicate modeling assumptions and results to senior technical stakeholders\nACADEMIC CREDENTIALS:\nBS/MS in Electrical Engineering, Computer Engineering, or related field\nLOCATION: Austin, TX\nThis role is not eligible for visa sponsorship.\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.\nTHE ROLE:\nWe are seeking a Senior Power Modeling Engineer to drive pre-silicon power modeling and analysis for AMD’s next-generation Embedded x86 SoC platforms. This role plays a critical part in defining use-case-driven power expectations, building SoC-level power models from IP inputs, and enabling informed EDC/TDC, voltage-frequency (VF), and PPA trade-off decisions early in the design cycle.\nTHE PERSON:\nThe ideal candidate brings deep hands-on experience with SoC power modeling methodologies and understands how IP-level power characteristics scale to full-chip behavior. This engineer will collaborate closely with SoC architects, power architects, performance teams, and silicon validation teams to ensure accurate power projections and influence architectural direction.\nKEY RESPONSIBILITIES:\nSoC & Use-Case Power Modeling\nDevelop and maintain SoC-level power models for Embedded x86 platforms using IP-level inputs (CPU, GPU, fabric, memory, and I/O).\n\nCreate use-case-driven power models representing automotive, industrial, edge computing, and customer-specific embedded workloads.\n\nTranslate real-world workloads into model inputs such as activity factors, concurrency, residency, and DVFS states.\n\nPower-Frequency & Electrical Modeling\nBuild and maintain Voltage-Frequency (VF) curves across operating corners.\nDerive and validate EDC / TDC / current limits based on modeled workloads and platform constraints.\nPerform sensitivity studies across frequency, voltage, workload mix, and power states.\nIP-to-SoC Model Integration\nIntegrate IP-level power models into cohesive SoC-level frameworks.\nEnsure consistency of assumptions across IPs (clocking, power states, gating, DVFS).\nIdentify gaps, inconsistencies, or inaccuracies in IP models and drive closure with IP teams.\nArchitecture & Trade-off Analysis\nPartner with SoC and power architects to influence early architectural decisions.\nEvaluate power/performance/area trade-offs for new features, configurations, and SKUs.\nSupport bounding-box analysis and product positioning decisions.\nCorrelation & Continuous Improvement\nSupport pre-silicon to post-silicon correlation of power models.\nRefine models using silicon data, profiling, and validation feedback.\nImprove modeling methodologies, accuracy targets, and documentation.\nPREFERRED EXPERIENCE:\nProfessional experience in power modeling, power estimation, or SoC power analysis\n\nStrong understanding of:\nSoC power architecture and DVFS\nStatic vs dynamic power components\nEDC / TDC / electrical and thermal constraints\nHands-on experience building SoC-level power models from IP-level models\nExperience creating and analyzing VF curves\nExperience with Embedded or Automotive SoCs\nFamiliarity with x86 CPU, GPU, memory, and fabric power behaviors\nExposure to power modeling tools, spreadsheets, or internal frameworks used for pre-silicon estimation\nExperience with workload-driven modeling and benchmark abstraction\nStrong analytical and scripting skills (Python preferred)\nAbility to work across architecture, IP, performance, and validation teams\nPrior involvement in power correlation with silicon\nAbility to clearly communicate modeling assumptions and results to senior technical stakeholders\nACADEMIC CREDENTIALS:\nBS/MS in Electrical Engineering, Computer Engineering, or related field\nLOCATION: Austin, TX\nThis role is not eligible for visa sponsorship.\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.","description_format":"text","description_chars":9413,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Incident Response","Processors, MCUs & AI Chips","Computer Components","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-10-20T09:44:57Z"}],"visa":[],"liveness":{"score":7,"band":"cold","label":"Long shot","p_open":1,"p_active":0.234,"p_room":0.28,"age_days":119,"expected_fill_days":15,"reasons":["conf:3","velocity","win:tail","crowd:brand"],"computed_at":"2026-10-21T05:46:15Z"},"pay":null,"html_url":"https://alion.io/job/amd-senior-soc-power-modeling-engineer","json_url":"https://alion.io/job/amd-senior-soc-power-modeling-engineer.json","meta":{"generated_at":"2026-10-22T04:15:14Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":4536,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-23T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":93},"rest":"https://alion.io/mcp/rest/get_company?id=93"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Famd-senior-soc-power-modeling-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Famd-senior-soc-power-modeling-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Famd-senior-soc-power-modeling-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/amd-senior-soc-power-modeling-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Famd-senior-soc-power-modeling-engineer"}]}