{"id":2910009,"url":"https://alion.io/job/amd-silicon-design-engineer-3","title":"Silicon Design Engineer","company":{"id":93,"name":"AMD","domain":"amd.com","url":"https://alion.io/company/amd","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Jibe","truth_index":{"grade":"B","score":80,"open_postings":160,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":20,"computed_at":"2026-10-23T05:54:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":null,"employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"explicit","locations":["Taipei, Taiwan"],"countries":["TW"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":16000,"max_usd":39000,"period":"year","method":"role_country_seniority_unknown","sample_n":23},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Formal Verification","optional":false},{"name":"Cadence JasperGold","optional":true},{"name":"Perl","optional":true},{"name":"Python","optional":true},{"name":"Synopsys VC Formal","optional":true},{"name":"SystemVerilog","optional":true},{"name":"UVM","optional":true},{"name":"Verilog","optional":true}],"status":"live","first_seen_at":"2026-10-14T03:20:00Z","employer_posted_date":"2026-10-20","last_verified_at":"2026-10-23T08:30:41Z","board_verified":true,"closed_at":null,"days_open":9,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":9},"description":"ADVANCE YOUR CAREER. ADVANCE THE WORLD.\nAt AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.\nWhether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Join us and, together, we’ll advance your career.\nSenior Formal Verification Engineer - USB\nThe Role\nWe are seeking a Senior Formal Verification Engineer to join AMD’s USB Design Verification team in Hsinchu or Taipei. You will develop and execute formal verification strategies for complex USB controller IP and related subsystems.\nThis is a hands-on technical role with opportunities to influence verification architecture, methodology, and sign-off quality. You will collaborate closely with design, architecture, simulation DV, and other engineering teams to identify high-risk behaviors, prove design correctness, and detect subtle bugs that are difficult to reach through simulation alone.\nThe Person\nThe ideal candidate has strong formal verification fundamentals, solid RTL design knowledge, and experience applying formal methods to complex digital designs. You are comfortable owning verification problems independently, debugging counterexamples, and communicating results across teams.\nExperience with USB or other high-speed interfaces is preferred, but deep formal verification expertise and the ability to learn new protocols are more important.\nKey Responsibilities\nDevelop formal verification plans and strategies for USB controller IP and related logic.\nBuild and maintain formal testbenches, assertions, assumptions, constraints, and reference models.\nApply formal methods to protocol control logic, state machines, data integrity, connectivity, ordering, arbitration, and error-handling behaviors.\nExecute property verification, connectivity checking, deadlock analysis, and formal coverage analysis.\nDebug counterexamples and collaborate with RTL designers to identify root causes and corrective actions.\nDefine measurable formal sign-off criteria and communicate verification status, gaps, and risks.\nIdentify verification areas where formal methods provide greater confidence or efficiency than simulation.\nImprove formal verification methodology, automation, scalability, and reuse across projects.\nReview specifications and microarchitecture documents to identify ambiguities and verification risks early.\nPartner with simulation DV teams to develop complementary formal and dynamic verification strategies.\nProvide technical guidance and mentoring to other engineers.\nPreferred Experience\nStrong experience in formal property verification of complex RTL designs.\nProficiency with SystemVerilog and SystemVerilog Assertions.\nHands-on experience with formal verification tools such as Cadence JasperGold, Synopsys VC Formal, Siemens Questa Formal, or equivalent.\nExperience developing formal environments, abstractions, constraints, checkers, and coverage models.\nStrong counterexample-debugging and root-cause-analysis skills.\nSolid understanding of digital design, finite-state machines, pipelines, clock/reset behavior, and bus protocols.\nExperience with Verilog/SystemVerilog RTL and scripting languages such as Python, Perl, Tcl, or shell.\nFamiliarity with simulation-based verification and UVM.\nKnowledge of USB 2.0, USB 3.x, USB4, xHCI, or another high-speed protocol is an advantage.\nExperience driving verification plans or methodology across multiple engineers is preferred.\nStrong written and verbal communication skills, with the ability to work effectively across global teams.\nAcademic Credentials\nBachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.\nRelevant industry experience in formal verification, design verification, or RTL design.\nLocation: Hsinchu or Taipei, Taiwan\n#LI-JW3\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.\nSenior Formal Verification Engineer - USB\nThe Role\nWe are seeking a Senior Formal Verification Engineer to join AMD’s USB Design Verification team in Hsinchu or Taipei. You will develop and execute formal verification strategies for complex USB controller IP and related subsystems.\nThis is a hands-on technical role with opportunities to influence verification architecture, methodology, and sign-off quality. You will collaborate closely with design, architecture, simulation DV, and other engineering teams to identify high-risk behaviors, prove design correctness, and detect subtle bugs that are difficult to reach through simulation alone.\nThe Person\nThe ideal candidate has strong formal verification fundamentals, solid RTL design knowledge, and experience applying formal methods to complex digital designs. You are comfortable owning verification problems independently, debugging counterexamples, and communicating results across teams.\nExperience with USB or other high-speed interfaces is preferred, but deep formal verification expertise and the ability to learn new protocols are more important.\nKey Responsibilities\nDevelop formal verification plans and strategies for USB controller IP and related logic.\nBuild and maintain formal testbenches, assertions, assumptions, constraints, and reference models.\nApply formal methods to protocol control logic, state machines, data integrity, connectivity, ordering, arbitration, and error-handling behaviors.\nExecute property verification, connectivity checking, deadlock analysis, and formal coverage analysis.\nDebug counterexamples and collaborate with RTL designers to identify root causes and corrective actions.\nDefine measurable formal sign-off criteria and communicate verification status, gaps, and risks.\nIdentify verification areas where formal methods provide greater confidence or efficiency than simulation.\nImprove formal verification methodology, automation, scalability, and reuse across projects.\nReview specifications and microarchitecture documents to identify ambiguities and verification risks early.\nPartner with simulation DV teams to develop complementary formal and dynamic verification strategies.\nProvide technical guidance and mentoring to other engineers.\nPreferred Experience\nStrong experience in formal property verification of complex RTL designs.\nProficiency with SystemVerilog and SystemVerilog Assertions.\nHands-on experience with formal verification tools such as Cadence JasperGold, Synopsys VC Formal, Siemens Questa Formal, or equivalent.\nExperience developing formal environments, abstractions, constraints, checkers, and coverage models.\nStrong counterexample-debugging and root-cause-analysis skills.\nSolid understanding of digital design, finite-state machines, pipelines, clock/reset behavior, and bus protocols.\nExperience with Verilog/SystemVerilog RTL and scripting languages such as Python, Perl, Tcl, or shell.\nFamiliarity with simulation-based verification and UVM.\nKnowledge of USB 2.0, USB 3.x, USB4, xHCI, or another high-speed protocol is an advantage.\nExperience driving verification plans or methodology across multiple engineers is preferred.\nStrong written and verbal communication skills, with the ability to work effectively across global teams.\nAcademic Credentials\nBachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.\nRelevant industry experience in formal verification, design verification, or RTL design.\nLocation: Hsinchu or Taipei, Taiwan\n#LI-JW3\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. 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