{"id":2909833,"url":"https://alion.io/job/amd-silicon-design-engineer","title":"Silicon Design Engineer","company":{"id":93,"name":"AMD","domain":"amd.com","url":"https://alion.io/company/amd","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Jibe","truth_index":{"grade":"B","score":80,"open_postings":157,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":15,"computed_at":"2026-10-22T06:10:10Z"}},"role":"Hardware","role_family":"Hardware","seniority":null,"employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Shanghai, China"],"countries":["CN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":19000,"max_usd":49000,"period":"year","method":"role_country_seniority_unknown","sample_n":167},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Cadence Innovus","optional":true},{"name":"Synopsys Fusion Compiler","optional":true}],"status":"live","first_seen_at":"2026-10-20T06:29:00Z","employer_posted_date":"2026-10-20","last_verified_at":"2026-10-22T11:40:18Z","board_verified":true,"closed_at":null,"days_open":2,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":2},"description":"ADVANCE YOUR CAREER. ADVANCE THE WORLD.\nAt AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.\nWhether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Join us and, together, we’ll advance your career.\nTHE ROLE:\nAs a member of the Fullchip Floorplan CAD team, you will help develop and enable advanced full-chip physical design methodologies for cutting-edge SoC designs. You will focus on Fullchip Floorplan flow development, working closely with project teams to deliver robust and scalable solutions for complex full-chip designs.\nAs a senior technical contributor, you will own key methodologies from concept through production deployment, drive technical direction, resolve complex design and flow challenges, and provide technical leadership across multiple engineering teams.\nTHE PERSON:\nThe successful candidate will be a highly motivated and experienced silicon design engineer with a strong background in physical design and CAD methodology development. The candidate should be able to independently drive complex technical problems, define solutions, and collaborate effectively across organizational and geographical boundaries.\nThe candidate will demonstrate strong technical leadership, ownership, communication, and problem-solving skills, with the ability to mentor engineers, influence technical decisions, and drive methodology improvements from initial development through successful production adoption.\nKEY RESPONSIBILITIES:\nOwn and drive major functions' methodology and flow development for large-scale SoC designs.\nDevelop methodologies to identify and optimize repeater and feedthrough requirements based on floorplan, connectivity, timing, hierarchy, and physical constraints.\nDrive complex technical issues to resolution across timing, long-distance interconnect, hierarchy, placement, congestion, and routability.\nDevelop robust and scalable CAD automation using Tcl, Python, Perl.\nDrive methodology and flow improvements from concept, prototyping and validation through production deployment.\nWork across Physical Design, Front-End Design/Integration, Timing teams to align requirements and ensure successful methodology integration.\nProvide technical leadership and guidance, conduct technical reviews, and mentor junior engineers.\nProactively identify methodology gaps, propose solutions, and drive continuous improvements in quality, scalability, runtime, robustness, and usability.\nSupport production projects, analyze complex flow issues, drive root-cause analysis, and develop systematic solutions to prevent recurrence.\nCommunicate technical strategy, implementation status, risks, and recommendations clearly to engineering stakeholders and leadership.\nPREFERRED EXPERIENCE:\nStrong understanding of ASIC physical design fundamentals, including floorplanning, placement, routing, timing analysis, hierarchical design, and timing closure.\nExperience with full-chip physical design, particularly long-distance interconnect optimization, repeater/buffer insertion, feedthrough planning, or related methodologies.\nExperience with physical design tools such as Cadence Innovus and/or Synopsys Fusion Compiler/ICC2.\nStrong programming and scripting skills in Tcl, Python, Perl.\nDemonstrated experience developing and deploying CAD/EDA methodologies and automation for large-scale SoC designs.\nProven ability to independently drive complex methodology development from problem definition and solution architecture through implementation, validation, and production deployment.\nExperience providing technical leadership, mentoring engineers, and driving cross-functional technical decisions.\nExcellent debugging and analytical skills with the ability to identify root causes and develop scalable solutions rather than testcase-specific fixes.\nStrong communication skills and demonstrated ability to collaborate with multiple engineering teams.\nACADEMIC CREDENTIALS:\nBachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.\n#LI-JW3\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.\nTHE ROLE:\nAs a member of the Fullchip Floorplan CAD team, you will help develop and enable advanced full-chip physical design methodologies for cutting-edge SoC designs. You will focus on Fullchip Floorplan flow development, working closely with project teams to deliver robust and scalable solutions for complex full-chip designs.\nAs a senior technical contributor, you will own key methodologies from concept through production deployment, drive technical direction, resolve complex design and flow challenges, and provide technical leadership across multiple engineering teams.\nTHE PERSON:\nThe successful candidate will be a highly motivated and experienced silicon design engineer with a strong background in physical design and CAD methodology development. The candidate should be able to independently drive complex technical problems, define solutions, and collaborate effectively across organizational and geographical boundaries.\nThe candidate will demonstrate strong technical leadership, ownership, communication, and problem-solving skills, with the ability to mentor engineers, influence technical decisions, and drive methodology improvements from initial development through successful production adoption.\nKEY RESPONSIBILITIES:\nOwn and drive major functions' methodology and flow development for large-scale SoC designs.\nDevelop methodologies to identify and optimize repeater and feedthrough requirements based on floorplan, connectivity, timing, hierarchy, and physical constraints.\nDrive complex technical issues to resolution across timing, long-distance interconnect, hierarchy, placement, congestion, and routability.\nDevelop robust and scalable CAD automation using Tcl, Python, Perl.\nDrive methodology and flow improvements from concept, prototyping and validation through production deployment.\nWork across Physical Design, Front-End Design/Integration, Timing teams to align requirements and ensure successful methodology integration.\nProvide technical leadership and guidance, conduct technical reviews, and mentor junior engineers.\nProactively identify methodology gaps, propose solutions, and drive continuous improvements in quality, scalability, runtime, robustness, and usability.\nSupport production projects, analyze complex flow issues, drive root-cause analysis, and develop systematic solutions to prevent recurrence.\nCommunicate technical strategy, implementation status, risks, and recommendations clearly to engineering stakeholders and leadership.\nPREFERRED EXPERIENCE:\nStrong understanding of ASIC physical design fundamentals, including floorplanning, placement, routing, timing analysis, hierarchical design, and timing closure.\nExperience with full-chip physical design, particularly long-distance interconnect optimization, repeater/buffer insertion, feedthrough planning, or related methodologies.\nExperience with physical design tools such as Cadence Innovus and/or Synopsys Fusion Compiler/ICC2.\nStrong programming and scripting skills in Tcl, Python, Perl.\nDemonstrated experience developing and deploying CAD/EDA methodologies and automation for large-scale SoC designs.\nProven ability to independently drive complex methodology development from problem definition and solution architecture through implementation, validation, and production deployment.\nExperience providing technical leadership, mentoring engineers, and driving cross-functional technical decisions.\nExcellent debugging and analytical skills with the ability to identify root causes and develop scalable solutions rather than testcase-specific fixes.\nStrong communication skills and demonstrated ability to collaborate with multiple engineering teams.\nACADEMIC CREDENTIALS:\nBachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.\n#LI-JW3\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.","description_format":"text","description_chars":10094,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Computer Components","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-10-20T09:19:33Z"}],"visa":[],"liveness":{"score":70,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.695,"p_room":1,"age_days":1,"expected_fill_days":15,"reasons":["conf:1","stale_co","wave","velocity","win:early","comp:brand"],"computed_at":"2026-10-22T06:10:10Z"},"pay":null,"html_url":"https://alion.io/job/amd-silicon-design-engineer","json_url":"https://alion.io/job/amd-silicon-design-engineer.json","meta":{"generated_at":"2026-10-22T14:12:33Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":13753,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-23T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":93},"rest":"https://alion.io/mcp/rest/get_company?id=93"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Famd-silicon-design-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Famd-silicon-design-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Famd-silicon-design-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/amd-silicon-design-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Famd-silicon-design-engineer"}]}