{"id":2911929,"url":"https://alion.io/job/amd-soc-dfx-scan-atpg-engineer","title":"SoC DFX Scan / ATPG Engineer","company":{"id":93,"name":"AMD","domain":"amd.com","url":"https://alion.io/company/amd","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Jibe","truth_index":{"grade":"B","score":80,"open_postings":157,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":15,"computed_at":"2026-10-22T06:10:10Z"}},"role":"Hardware","role_family":"Hardware","seniority":null,"employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Ottawa, Canada"],"countries":["CA"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":68000,"max_usd":134000,"period":"year","method":"role_country_seniority_unknown","sample_n":146},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":true},{"name":"Python","optional":true},{"name":"SystemVerilog","optional":true},{"name":"Verilog","optional":true}],"status":"live","first_seen_at":"2026-08-04T20:54:00Z","employer_posted_date":"2026-10-20","last_verified_at":"2026-10-22T04:24:27Z","board_verified":true,"closed_at":null,"days_open":78,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":78},"description":"WHAT YOU DO AT AMD CHANGES EVERYTHING\nAt AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gamingand embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuityand a shared passion to create something extraordinary. When you join AMD, you’lldiscover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.Together, we advance your career.\n THE ROLE:\nAs part of the SoC (System-on-Chip) Design-for-Test (DFT) team, you will be responsible for implementing, verifying, optimizing, and deploying advanced DFT solutions across next-generation products. You will work closely with architecture, design, verification, physical design, and product engineering teams to ensure high-quality scan insertion and ATPG execution for complex SoCs.\nThis role offers the opportunity to drive test architecture, improve manufacturability and test quality, support silicon bring-up activities, and contribute to scalable DFT methodologies across a range of products.\nTHE PERSON:\nYou are a motivated engineer with a strong understanding of DFT fundamentals and ASIC design flows. You enjoy solving complex technical challenges, applying strong analytical and debugging skills, and working collaboratively across multiple engineering disciplines. You communicate effectively, take ownership of problems, and maintain a strong focus on quality, coverage, and manufacturability.\nKEY RESPONSIBILITIES:\nDrive end-to-end SoC-level scan insertion, DFT implementation, and ATPG execution.\nDevelop and optimize scan architectures, scan chains, test compression, and ATPG strategies.\nAnalyze scan coverage and ATPG results to improve test quality and coverage.\nSupport ATPG retargeting and hierarchical test integration methodologies.\nDebug scan, ATPG, simulation, and emulation issues from block level through full-chip integration.\nDevelop and validate methodologies for stuck-at, transition, at-speed, and diagnostic pattern generation.\nCollaborate with design, verification, physical design, CAD, and product engineering teams to resolve DFT-related challenges.\nSupport silicon bring-up, manufacturing test development, yield improvement, and failure analysis activities.\nContribute to DFT planning and implementation of technologies such as scan compression, memory built-in self-test (MBIST), logic built-in self-test (LBIST), PLL-based at-speed testing, and on-chip debug infrastructure.\nDevelop automation and scripting solutions to improve DFT productivity, quality, and scalability.\nPREFERRED EXPERIENCE:\nExperience with scan insertion, ATPG, and DFT methodologies.\nStrong knowledge of digital design fundamentals and ASIC development flows.\nExperience with test compression technologies and hierarchical ATPG flows.\nExperience debugging gate-level simulation, ATPG validation, and SoC integration issues.\nFamiliarity with Verilog/SystemVerilog and digital logic design.\nExperience with scripting languages such as Python, Perl, Tcl, or Shell.\nExperience with SoC-level ATPG retargeting methodologies.\nFamiliarity with emulation-based DFT validation and debug.\nExperience with silicon bring-up, diagnosis, and yield analysis.\nKnowledge of MBIST, LBIST, JTAG/IJTAG, Streaming Scan Network (SSN), or other advanced DFT methodologies.\nExperience supporting large-scale GPU, CPU, AI accelerator, or complex ASIC development.\nACADEMIC CREDENTIALS:\nBachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.\nLOCATIONS:\nMarkham, Ottawa\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.\nTHE ROLE:\nAs part of the SoC (System-on-Chip) Design-for-Test (DFT) team, you will be responsible for implementing, verifying, optimizing, and deploying advanced DFT solutions across next-generation products. You will work closely with architecture, design, verification, physical design, and product engineering teams to ensure high-quality scan insertion and ATPG execution for complex SoCs.\nThis role offers the opportunity to drive test architecture, improve manufacturability and test quality, support silicon bring-up activities, and contribute to scalable DFT methodologies across a range of products.\nTHE PERSON:\nYou are a motivated engineer with a strong understanding of DFT fundamentals and ASIC design flows. You enjoy solving complex technical challenges, applying strong analytical and debugging skills, and working collaboratively across multiple engineering disciplines. You communicate effectively, take ownership of problems, and maintain a strong focus on quality, coverage, and manufacturability.\nKEY RESPONSIBILITIES:\nDrive end-to-end SoC-level scan insertion, DFT implementation, and ATPG execution.\nDevelop and optimize scan architectures, scan chains, test compression, and ATPG strategies.\nAnalyze scan coverage and ATPG results to improve test quality and coverage.\nSupport ATPG retargeting and hierarchical test integration methodologies.\nDebug scan, ATPG, simulation, and emulation issues from block level through full-chip integration.\nDevelop and validate methodologies for stuck-at, transition, at-speed, and diagnostic pattern generation.\nCollaborate with design, verification, physical design, CAD, and product engineering teams to resolve DFT-related challenges.\nSupport silicon bring-up, manufacturing test development, yield improvement, and failure analysis activities.\nContribute to DFT planning and implementation of technologies such as scan compression, memory built-in self-test (MBIST), logic built-in self-test (LBIST), PLL-based at-speed testing, and on-chip debug infrastructure.\nDevelop automation and scripting solutions to improve DFT productivity, quality, and scalability.\nPREFERRED EXPERIENCE:\nExperience with scan insertion, ATPG, and DFT methodologies.\nStrong knowledge of digital design fundamentals and ASIC development flows.\nExperience with test compression technologies and hierarchical ATPG flows.\nExperience debugging gate-level simulation, ATPG validation, and SoC integration issues.\nFamiliarity with Verilog/SystemVerilog and digital logic design.\nExperience with scripting languages such as Python, Perl, Tcl, or Shell.\nExperience with SoC-level ATPG retargeting methodologies.\nFamiliarity with emulation-based DFT validation and debug.\nExperience with silicon bring-up, diagnosis, and yield analysis.\nKnowledge of MBIST, LBIST, JTAG/IJTAG, Streaming Scan Network (SSN), or other advanced DFT methodologies.\nExperience supporting large-scale GPU, CPU, AI accelerator, or complex ASIC development.\nACADEMIC CREDENTIALS:\nBachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.\nLOCATIONS:\nMarkham, Ottawa\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. 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