{"id":2909965,"url":"https://alion.io/job/amd-soc-physical-integration-engineer","title":"SoC Physical Integration Engineer","company":{"id":93,"name":"AMD","domain":"amd.com","url":"https://alion.io/company/amd","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Jibe","truth_index":{"grade":"B","score":75,"open_postings":162,"ghost_share":0,"stale_share":0.994,"repost_share":0,"time_to_fill_p50_days":29,"computed_at":"2026-10-25T05:49:26Z"}},"role":"Hardware","role_family":"Hardware","seniority":null,"employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["San Jose, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":120000,"max_usd":271000,"period":"year","method":"role_country_seniority_unknown","sample_n":2844},"experience_years_min":null,"visa_sponsorship":true,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Linux","optional":true},{"name":"Perl","optional":true},{"name":"Python","optional":true},{"name":"Synopsys Fusion Compiler","optional":true},{"name":"Unix","optional":true},{"name":"Verilog","optional":true}],"status":"live","first_seen_at":"2026-10-15T17:07:00Z","employer_posted_date":"2026-10-20","last_verified_at":"2026-10-25T09:43:52Z","board_verified":true,"closed_at":null,"days_open":9,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":9},"description":"ADVANCE YOUR CAREER. ADVANCE THE WORLD.\nAt AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.\nWhether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Join us and, together, we’ll advance your career.\nTHE ROLE:\nAMD’s Adaptive Embedded Computing Group (AECG) develops innovative products that combine high-performance, energy-efficient processors, advanced neural engines, graphics processors, and adaptive computing technologies with programmable logic to enable next-generation edge computing solutions. From autonomous vehicles and industrial robotics to intelligent healthcare devices, AMD AECG is helping redefine the future of intelligent edge computing.\nTHE PERSON:\nAs a member of the SoC Physical Integration team, you will collaborate closely with cross-functional engineering teams, including Architecture, Design, CAD, Software, and Product Engineering, across multiple geographies. You will contribute to the physical and electrical verification, integration, and tape-out of AMD SoC FPGA/ACAP devices.\nKEY RESPONSIBILITIES:\nDefine and develop flows and methodologies for chip-level integration.\nDevelop tools and automation to enhance design verification and engineering efficiency.\nDesign, verify, and integrate FPGA/ACAP sub-blocks, including RTL and custom design.\nCoordinate activities across design teams to enable seamless chip-level integration.\nExecute chip-level physical verification.\nExecute chip-level electrical verification.\nPREFERRED EXPERIENCE:\nSolid understanding of FPGA architectures.\nHands-on experience with advanced process nodes, including leading-edge 2nm and 3nm technologies.\nIn-depth knowledge of 2.5D and 3D interposer technologies.\nHands-on experience with physical implementation using one or more industry- standard physical design tools, such as Virtuoso, ICC2, Fusion Compiler (FC), Innovus, or comparable tools.\nStrong foundation in circuit design, including hands-on simulation experience with SPICE and Verilog.\nKnowledge of or practical experience with Place and Route (P&R) tools and methodologies.\nStrong debugging, analytical, and problem-solving skills.\nProficiency in scripting languages such as Perl, Python, TCL, C-shell, Make, or other relevant scripting languages.\nExperience working in Unix/Linux environments, including data management and job control.\nExcellent written and verbal communication skills, with the ability to collaborate effectively across cross-functional and geographically distributed teams.\nACADEMIC CREDENTIALS:\nBachelor’s or Master’s degree in Electrical Engineering or an equivalent field.\nLOCATION: San Jose, CA\nThis role is not eligible for visa sponsorship.\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.\nTHE ROLE:\nAMD’s Adaptive Embedded Computing Group (AECG) develops innovative products that combine high-performance, energy-efficient processors, advanced neural engines, graphics processors, and adaptive computing technologies with programmable logic to enable next-generation edge computing solutions. From autonomous vehicles and industrial robotics to intelligent healthcare devices, AMD AECG is helping redefine the future of intelligent edge computing.\nTHE PERSON:\nAs a member of the SoC Physical Integration team, you will collaborate closely with cross-functional engineering teams, including Architecture, Design, CAD, Software, and Product Engineering, across multiple geographies. You will contribute to the physical and electrical verification, integration, and tape-out of AMD SoC FPGA/ACAP devices.\nKEY RESPONSIBILITIES:\nDefine and develop flows and methodologies for chip-level integration.\nDevelop tools and automation to enhance design verification and engineering efficiency.\nDesign, verify, and integrate FPGA/ACAP sub-blocks, including RTL and custom design.\nCoordinate activities across design teams to enable seamless chip-level integration.\nExecute chip-level physical verification.\nExecute chip-level electrical verification.\nPREFERRED EXPERIENCE:\nSolid understanding of FPGA architectures.\nHands-on experience with advanced process nodes, including leading-edge 2nm and 3nm technologies.\nIn-depth knowledge of 2.5D and 3D interposer technologies.\nHands-on experience with physical implementation using one or more industry- standard physical design tools, such as Virtuoso, ICC2, Fusion Compiler (FC), Innovus, or comparable tools.\nStrong foundation in circuit design, including hands-on simulation experience with SPICE and Verilog.\nKnowledge of or practical experience with Place and Route (P&R) tools and methodologies.\nStrong debugging, analytical, and problem-solving skills.\nProficiency in scripting languages such as Perl, Python, TCL, C-shell, Make, or other relevant scripting languages.\nExperience working in Unix/Linux environments, including data management and job control.\nExcellent written and verbal communication skills, with the ability to collaborate effectively across cross-functional and geographically distributed teams.\nACADEMIC CREDENTIALS:\nBachelor’s or Master’s degree in Electrical Engineering or an equivalent field.\nLOCATION: San Jose, CA\nThis role is not eligible for visa sponsorship.\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.","description_format":"text","description_chars":7344,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":true},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Incident Response","Processors, MCUs & AI Chips","Computer Components","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-10-20T09:19:33Z"}],"visa":[],"liveness":{"score":59,"band":"ok","label":"Likely open","p_open":1,"p_active":0.587,"p_room":1,"age_days":9,"expected_fill_days":29,"reasons":["conf:0","stale_co","velocity","win:early","comp:brand"],"computed_at":"2026-10-25T05:49:26Z"},"pay":null,"html_url":"https://alion.io/job/amd-soc-physical-integration-engineer","json_url":"https://alion.io/job/amd-soc-physical-integration-engineer.json","meta":{"generated_at":"2026-10-25T12:12:31Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":17659,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-26T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":93},"rest":"https://alion.io/mcp/rest/get_company?id=93"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Famd-soc-physical-integration-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Famd-soc-physical-integration-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Famd-soc-physical-integration-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/amd-soc-physical-integration-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Famd-soc-physical-integration-engineer"}]}