{"id":2911295,"url":"https://alion.io/job/amd-sr-design-verification-engineer","title":"Sr. Design Verification Engineer","company":{"id":93,"name":"AMD","domain":"amd.com","url":"https://alion.io/company/amd","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Jibe","truth_index":{"grade":"A","score":95,"open_postings":10,"ghost_share":0,"stale_share":0.2,"repost_share":0,"time_to_fill_p50_days":42,"computed_at":"2026-11-04T06:34:25Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Santa Clara, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":149000,"max_usd":275000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":1517},"experience_years_min":null,"visa_sponsorship":true,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Azure","optional":false},{"name":"C++","optional":false},{"name":"Formal Verification","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Synopsys HAPS","optional":false},{"name":"Synopsys Verdi","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false}],"status":"closed","first_seen_at":"2026-09-11T17:38:00Z","employer_posted_date":"2026-10-31","last_verified_at":"2026-11-04T01:47:01Z","board_verified":false,"closed_at":"2026-11-04T01:47:01Z","days_open":53,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":53},"description":"WHAT YOU DO AT AMD CHANGES EVERYTHING\nAt AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gamingand embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuityand a shared passion to create something extraordinary. When you join AMD, you’lldiscover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.Together, we advance your career.\nTHE ROLE:\nAMD’s Network Technologies Solutions Group (NTSG) is a leading provider of advanced data center networking technology. Our distributed services platform expands AMD’s data center product portfolio with a high-performance DPU and software stack deployed at scale across major cloud and enterprise environments, including Goldman Sachs, IBM Cloud, Microsoft Azure, and Oracle.\nTHE PERSON:\nWe are seeking a high-impact Design Verification Engineer with strong technical depth, ownership, and the ability to drive verification closure on complex, high-performance ASIC designs.\nThe ideal candidate brings hands-on verification expertise, excels in debugging intricate architecture/RTL issues, and is comfortable leading verification efforts across IP, subsystem, and SoC levels.\nYou will work in a fast-paced, highly collaborative environment and contribute directly to the success of next-generation AMD networking products.\nKEY RESPONSIBILITIES:\nVerification Architecture & Testbench Development\nDevelop robust UVM-based testbench architectures for IP, subsystem, and SoC-level verification.\nDrive test plan creation, feature mapping, and coverage strategy for complex networking and data-path IP.\nDevelop high-quality SystemVerilog components: stimulus generators, agents, BFMs/transactors, scoreboards, checkers, assertions, and functional coverage models.\nExecution, Debug & Closure\nOwn execution of verification plans, regression triage, and debug of architectural, functional, and performance issues.\nRoot-cause complex failures across RTL, testbench, interfaces (PCIe/DDR/Ethernet), and system interactions.\nOptimize simulations, coverage closure, and verification sign-off methodology.\nTools & Methodology\nUse industry-standard simulation, debug, and analysis tools (VCS, Verdi/DVE, coverage tools, waveform analysis suites).\nContribute to verification methodology improvements, automation, and infrastructure enhancements (Python/Tcl/Make).\nCross-Functional Collaboration\nCollaborate closely with RTL design, architecture, validation, firmware, and emulation/HAPS teams to ensure high-quality deliverables.\nParticipate in design reviews, micro-architecture definition, and bring a verification perspective into early design stages.\nMentor junior engineers and provide technical leadership within the verification team.\nLANGUAGES & TOOLS\nRequired\nExpert-level knowledge of SystemVerilog and UVM\nStrong hands-on experience with SystemVerilog simulators (VCS preferred) and waveform debuggers (Verdi/DVE)\nProven experience in verifying complex IP/subsystems with test plans, coverage, and constrained-random methodologies\nStrong debug skills across architecture, RTL, and testbench layers\nExperience with industry protocols such as PCIe, AXI, Ethernet, DDR, DMA engines, or similar data-path components\nScripting skills in Python, Perl, Shell, Tcl, or equivalent for automation and infrastructure\nPreferred\nExperience with performance verification, power-aware verification (UPF), or formal verification\nFamiliarity with FPGA/HAPS-based validation and acceleration flows\nUnderstanding of networking or high-speed I/O pipelines\nExposure to architectural modeling or C/C++ reference models\nPREFERRED QUALIFICATIONS:\nStrong analytical and problem-solving abilities with a proven track record of debugging complex issues\nAbility to lead verification tasks independently and drive cross-team closure\nExcellent verbal and written communication skills\nComfortable working in a fast-paced, collaborative, multi-site environment\nAbility to mentor and guide junior DV engineers\nACADEMIC CREDENTIALS\nBachelor’s Degree in Electrical/Computer Engineering or related field, Master’s Preferred\nLOCATION:\nHybrid in Santa Clara, CA or Austin, TX\nThis role is not eligible for visa sponsorship.\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.\nTHE ROLE:\nAMD’s Network Technologies Solutions Group (NTSG) is a leading provider of advanced data center networking technology. Our distributed services platform expands AMD’s data center product portfolio with a high-performance DPU and software stack deployed at scale across major cloud and enterprise environments, including Goldman Sachs, IBM Cloud, Microsoft Azure, and Oracle.\nTHE PERSON:\nWe are seeking a high-impact Design Verification Engineer with strong technical depth, ownership, and the ability to drive verification closure on complex, high-performance ASIC designs.\nThe ideal candidate brings hands-on verification expertise, excels in debugging intricate architecture/RTL issues, and is comfortable leading verification efforts across IP, subsystem, and SoC levels.\nYou will work in a fast-paced, highly collaborative environment and contribute directly to the success of next-generation AMD networking products.\nKEY RESPONSIBILITIES:\nVerification Architecture & Testbench Development\nDevelop robust UVM-based testbench architectures for IP, subsystem, and SoC-level verification.\nDrive test plan creation, feature mapping, and coverage strategy for complex networking and data-path IP.\nDevelop high-quality SystemVerilog components: stimulus generators, agents, BFMs/transactors, scoreboards, checkers, assertions, and functional coverage models.\nExecution, Debug & Closure\nOwn execution of verification plans, regression triage, and debug of architectural, functional, and performance issues.\nRoot-cause complex failures across RTL, testbench, interfaces (PCIe/DDR/Ethernet), and system interactions.\nOptimize simulations, coverage closure, and verification sign-off methodology.\nTools & Methodology\nUse industry-standard simulation, debug, and analysis tools (VCS, Verdi/DVE, coverage tools, waveform analysis suites).\nContribute to verification methodology improvements, automation, and infrastructure enhancements (Python/Tcl/Make).\nCross-Functional Collaboration\nCollaborate closely with RTL design, architecture, validation, firmware, and emulation/HAPS teams to ensure high-quality deliverables.\nParticipate in design reviews, micro-architecture definition, and bring a verification perspective into early design stages.\nMentor junior engineers and provide technical leadership within the verification team.\nLANGUAGES & TOOLS\nRequired\nExpert-level knowledge of SystemVerilog and UVM\nStrong hands-on experience with SystemVerilog simulators (VCS preferred) and waveform debuggers (Verdi/DVE)\nProven experience in verifying complex IP/subsystems with test plans, coverage, and constrained-random methodologies\nStrong debug skills across architecture, RTL, and testbench layers\nExperience with industry protocols such as PCIe, AXI, Ethernet, DDR, DMA engines, or similar data-path components\nScripting skills in Python, Perl, Shell, Tcl, or equivalent for automation and infrastructure\nPreferred\nExperience with performance verification, power-aware verification (UPF), or formal verification\nFamiliarity with FPGA/HAPS-based validation and acceleration flows\nUnderstanding of networking or high-speed I/O pipelines\nExposure to architectural modeling or C/C++ reference models\nPREFERRED QUALIFICATIONS:\nStrong analytical and problem-solving abilities with a proven track record of debugging complex issues\nAbility to lead verification tasks independently and drive cross-team closure\nExcellent verbal and written communication skills\nComfortable working in a fast-paced, collaborative, multi-site environment\nAbility to mentor and guide junior DV engineers\nACADEMIC CREDENTIALS\nBachelor’s Degree in Electrical/Computer Engineering or related field, Master’s Preferred\nLOCATION:\nHybrid in Santa Clara, CA or Austin, TX\nThis role is not eligible for visa sponsorship.\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.","description_format":"text","description_chars":10221,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":true},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Computer Components","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-10-20T09:36:36Z"},{"event":"close","at":"2026-10-31T13:38:47Z"},{"event":"reopen","at":"2026-10-31T17:13:40Z"},{"event":"close","at":"2026-11-04T01:47:01Z"}],"visa":[],"liveness":null,"pay":null,"html_url":"https://alion.io/job/amd-sr-design-verification-engineer","json_url":"https://alion.io/job/amd-sr-design-verification-engineer.json","meta":{"generated_at":"2026-11-05T00:07:16Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":75,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-06T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":93},"rest":"https://alion.io/mcp/rest/get_company?id=93"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Famd-sr-design-verification-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Famd-sr-design-verification-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Famd-sr-design-verification-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/amd-sr-design-verification-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Famd-sr-design-verification-engineer"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":2911295}},{"tool":"search_jobs","arguments":{"company":"amd.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":2911295},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. Docs: https://alion.io/developers"}}