Sr DFT/ATPG Engineer–Mixed-Signal IP

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THE ROLE:

The Scan ATPG Engineer will own scan architecture and validation strategy for analog and mixed-signal intellectual property (IP). This role is responsible for delivering production-quality test patterns and supporting silicon bring-up and debug of those patterns. The engineer will collaborate across analog design, digital design, verification, DFT, physical design, product engineering, and test engineering teams to deliver robust, manufacturable solutions that achieve high test quality.

THE PERSON:

The ideal candidate brings strong technical judgment, ownership, and a collaborative approach to solving complex engineering challenges. They communicate technical information clearly to different audiences and work effectively across functions to build alignment around practical technical solutions. They are curious, adaptable, and committed to continuous learning and improvement, with the ability to lead technical initiatives and contribute effectively within a collaborative engineering environment.

KEY RESPONSIBILITIES:

• Define and document scan architectures for analog and mixed-signal IP, considering test coverage, implementation complexity, timing, power, area, and integration requirements.
• Develop and maintain ATPG models for custom digital, analog-interface, and mixed-signal circuitry to enable accurate fault modeling and pattern generation.
• Validate scan-stitched gate-level netlists, including scan-chain connectivity, test-mode controls, clocks, resets, constraints, and cross-domain behavior.
• Analyze, debug, and improve test coverage to achieve appropriate coverage targets across multiple fault models, including stuck-at and transition-delay faults.
• Perform zero-delay and SDF-annotated gate-level simulations of ATPG patterns; identify and resolve simulation failures, timing issues, X-propagation, and model or netlist mismatches.
• Own the generation, validation, documentation, delivery, and lifecycle management of production test patterns.
• Partner with product and test engineering teams to support pattern deployment, silicon bring-up, yield learning, failure analysis, and post-silicon debug.
• Collaborate with cross-functional teams to identify and resolve testability issues and contribute to improvements in architecture, methodology, automation, and quality.

PREFERRED EXPERIENCE:

• Experience with scan design, ATPG, fault simulation, coverage analysis, and pattern validation for complex IP or SoC designs.
• Experience applying DFT methodologies to analog and mixed-signal IP, including modeling custom circuitry and interfaces for ATPG.
• Experience with industry-standard ATPG, gate-level simulation, waveform-debug, and DFT verification tools.
• Knowledge of multiple fault models, such as stuck-at, transition-delay, cell-aware, bridging, or comparable advanced defect-oriented models.
• Experience identifying and resolving scan-chain, netlist, constraint, clocking, reset, timing, and X-propagation issues.
• Knowledge of zero-delay and SDF-annotated simulation flows and production pattern formats.
• Experience supporting silicon bring-up, production test deployment, yield learning, post-silicon failure analysis, or closely related activities.
• Programming or scripting experience with Python, Perl, Tcl, or comparable languages for flow development, data analysis, or automation.
• Demonstrated ability to lead technical work, collaborate across functions, build alignment around technical decisions, and communicate technical concepts to a range of stakeholders.

ACADEMIC CREDENTIALS:

• Bachelor’s or master’s degree in electrical engineering, Computer Engineering, a closely related technical field, or equivalent practical experience.

This role is not eligible for visa sponsorship.

#LI-DP1

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.

THE ROLE:

The Scan ATPG Engineer will own scan architecture and validation strategy for analog and mixed-signal intellectual property (IP). This role is responsible for delivering production-quality test patterns and supporting silicon bring-up and debug of those patterns. The engineer will collaborate across analog design, digital design, verification, DFT, physical design, product engineering, and test engineering teams to deliver robust, manufacturable solutions that achieve high test quality.

THE PERSON:

The ideal candidate brings strong technical judgment, ownership, and a collaborative approach to solving complex engineering challenges. They communicate technical information clearly to different audiences and work effectively across functions to build alignment around practical technical solutions. They are curious, adaptable, and committed to continuous learning and improvement, with the ability to lead technical initiatives and contribute effectively within a collaborative engineering environment.

KEY RESPONSIBILITIES:

• Define and document scan architectures for analog and mixed-signal IP, considering test coverage, implementation complexity, timing, power, area, and integration requirements.
• Develop and maintain ATPG models for custom digital, analog-interface, and mixed-signal circuitry to enable accurate fault modeling and pattern generation.
• Validate scan-stitched gate-level netlists, including scan-chain connectivity, test-mode controls, clocks, resets, constraints, and cross-domain behavior.
• Analyze, debug, and improve test coverage to achieve appropriate coverage targets across multiple fault models, including stuck-at and transition-delay faults.
• Perform zero-delay and SDF-annotated gate-level simulations of ATPG patterns; identify and resolve simulation failures, timing issues, X-propagation, and model or netlist mismatches.
• Own the generation, validation, documentation, delivery, and lifecycle management of production test patterns.
• Partner with product and test engineering teams to support pattern deployment, silicon bring-up, yield learning, failure analysis, and post-silicon debug.
• Collaborate with cross-functional teams to identify and resolve testability issues and contribute to improvements in architecture, methodology, automation, and quality.

PREFERRED EXPERIENCE:

• Experience with scan design, ATPG, fault simulation, coverage analysis, and pattern validation for complex IP or SoC designs.
• Experience applying DFT methodologies to analog and mixed-signal IP, including modeling custom circuitry and interfaces for ATPG.
• Experience with industry-standard ATPG, gate-level simulation, waveform-debug, and DFT verification tools.
• Knowledge of multiple fault models, such as stuck-at, transition-delay, cell-aware, bridging, or comparable advanced defect-oriented models.
• Experience identifying and resolving scan-chain, netlist, constraint, clocking, reset, timing, and X-propagation issues.
• Knowledge of zero-delay and SDF-annotated simulation flows and production pattern formats.
• Experience supporting silicon bring-up, production test deployment, yield learning, post-silicon failure analysis, or closely related activities.
• Programming or scripting experience with Python, Perl, Tcl, or comparable languages for flow development, data analysis, or automation.
• Demonstrated ability to lead technical work, collaborate across functions, build alignment around technical decisions, and communicate technical concepts to a range of stakeholders.

ACADEMIC CREDENTIALS:

• Bachelor’s or master’s degree in electrical engineering, Computer Engineering, a closely related technical field, or equivalent practical experience.

This role is not eligible for visa sponsorship.

#LI-DP1

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.