{"id":2912288,"url":"https://alion.io/job/amd-sr-fellow-memory-phy-architect","title":"Sr. Fellow -- Memory PHY Architect","company":{"id":93,"name":"AMD","domain":"amd.com","url":"https://alion.io/company/amd","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Jibe","truth_index":{"grade":"B","score":80,"open_postings":160,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":20,"computed_at":"2026-10-23T05:54:15Z"}},"role":"Science & Research","role_family":"Science & Research","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Santa Clara, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":98000,"max_usd":261000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":584},"experience_years_min":15,"visa_sponsorship":true,"relocation_package":false,"has_equity":false,"technologies":[],"status":"live","first_seen_at":"2025-12-26T19:40:00Z","employer_posted_date":"2026-10-20","last_verified_at":"2026-10-23T08:30:41Z","board_verified":true,"closed_at":null,"days_open":300,"trust":{"level":"stale","repost_count":0,"flags":["stale"],"days_open":300},"description":"WHAT YOU DO AT AMD CHANGES EVERYTHING\nAt AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gamingand embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuityand a shared passion to create something extraordinary. When you join AMD, you’lldiscover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.Together, we advance your career.\nTHE ROLE:\nThis role offers a rare opportunity for a senior technical leader to shape the future of memory interface technology at scale. As a key architect within the AMD Circuit Technology Design Group, you will influence the definition, architecture, and delivery of next-generation Memory PHY solutions in advanced CMOS technologies. The focus is on long-term impact: setting technical direction, guiding critical design decisions, and enabling teams to deliver differentiated mixed-signal IP across future SoCs.\nThis position is well suited for technologists who value deep technical ownership, architectural influence, and the ability to leave a lasting technical legacy-without requiring people-management as a primary responsibility.\nTHE PERSON:\nYou are a highly respected engineer or architect known for solving difficult problems and raising the technical bar around you. You bring perspective earned from experience, approach challenges with curiosity and pragmatism, and engage others through thoughtful collaboration rather than authority. You are comfortable operating with ambiguity, influencing across organizations, and contributing at both strategic and hands-on technical levels.\nKEY RESPONSIBILITIES:\nServe as a senior technical authority and architect for Memory PHY technology, shaping long-range roadmaps and architectural direction.\nDefine and evolve architectures and specifications for advanced Memory PHYs, including DDR, LPDDR, GDDR, and HBM.\nDrive innovation in high-speed I/O circuit design, system-level analysis, power integrity, and signal integrity.\nPartner with cross-functional teams across Circuit Design, Layout, Logic Design, Physical Design, Firmware, Design Verification, and Post-Silicon organizations worldwide.\nInfluence design quality and execution through design reviews, technical mentorship, and principled tradeoff decisions.\nSupport post-silicon bring-up, validation, characterization, optimization, and product readiness.\nCommunicate complex technical concepts clearly to senior technical peers, leadership, and stakeholders.\nMentor and advise engineers and architects, contributing to a strong and inclusive technical community.\nPREFERRED EXPERIENCE:\nSustained technical impact on production Memory PHYs or high-speed I/O IP at advanced technology nodes.\nExperience owning or shaping architecture across multiple successful tape-outs.\nDeep expertise in high-speed analog and mixed-signal design, memory protocols, and system-level considerations.\nStrong understanding of advanced CMOS technologies and modern design methodologies.\nTrack record of making sound technical decisions in complex, high-risk design spaces.\nAbility to influence without formal authority and collaborate effectively across organizational boundaries.\nACADEMIC CREDENTIALS:\nAdvanced degree in Electrical Engineering or related field preferred, or equivalent professional experience.\nTypically, 15+ years of experience in high-speed analog, mixed-signal, or memory PHY design.\nLOCATION:\nFlexible - Bay Area, CA; Boston, MA; Austin, TX; or Toronto, Canada.\nThis role is not eligible for visa sponsorship.\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.\nTHE ROLE:\nThis role offers a rare opportunity for a senior technical leader to shape the future of memory interface technology at scale. As a key architect within the AMD Circuit Technology Design Group, you will influence the definition, architecture, and delivery of next-generation Memory PHY solutions in advanced CMOS technologies. The focus is on long-term impact: setting technical direction, guiding critical design decisions, and enabling teams to deliver differentiated mixed-signal IP across future SoCs.\nThis position is well suited for technologists who value deep technical ownership, architectural influence, and the ability to leave a lasting technical legacy-without requiring people-management as a primary responsibility.\nTHE PERSON:\nYou are a highly respected engineer or architect known for solving difficult problems and raising the technical bar around you. You bring perspective earned from experience, approach challenges with curiosity and pragmatism, and engage others through thoughtful collaboration rather than authority. You are comfortable operating with ambiguity, influencing across organizations, and contributing at both strategic and hands-on technical levels.\nKEY RESPONSIBILITIES:\nServe as a senior technical authority and architect for Memory PHY technology, shaping long-range roadmaps and architectural direction.\nDefine and evolve architectures and specifications for advanced Memory PHYs, including DDR, LPDDR, GDDR, and HBM.\nDrive innovation in high-speed I/O circuit design, system-level analysis, power integrity, and signal integrity.\nPartner with cross-functional teams across Circuit Design, Layout, Logic Design, Physical Design, Firmware, Design Verification, and Post-Silicon organizations worldwide.\nInfluence design quality and execution through design reviews, technical mentorship, and principled tradeoff decisions.\nSupport post-silicon bring-up, validation, characterization, optimization, and product readiness.\nCommunicate complex technical concepts clearly to senior technical peers, leadership, and stakeholders.\nMentor and advise engineers and architects, contributing to a strong and inclusive technical community.\nPREFERRED EXPERIENCE:\nSustained technical impact on production Memory PHYs or high-speed I/O IP at advanced technology nodes.\nExperience owning or shaping architecture across multiple successful tape-outs.\nDeep expertise in high-speed analog and mixed-signal design, memory protocols, and system-level considerations.\nStrong understanding of advanced CMOS technologies and modern design methodologies.\nTrack record of making sound technical decisions in complex, high-risk design spaces.\nAbility to influence without formal authority and collaborate effectively across organizational boundaries.\nACADEMIC CREDENTIALS:\nAdvanced degree in Electrical Engineering or related field preferred, or equivalent professional experience.\nTypically, 15+ years of experience in high-speed analog, mixed-signal, or memory PHY design.\nLOCATION:\nFlexible - Bay Area, CA; Boston, MA; Austin, TX; or Toronto, Canada.\nThis role is not eligible for visa sponsorship.\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.","description_format":"text","description_chars":8895,"description_truncated":false,"requirements":{"experience_years_min":15,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Computer Components","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-10-20T09:52:16Z"}],"visa":[],"liveness":{"score":5,"band":"cold","label":"Long shot","p_open":1,"p_active":0.183,"p_room":0.28,"age_days":300,"expected_fill_days":20,"reasons":["conf:1","stale_co","velocity","win:tail","crowd:brand"],"computed_at":"2026-10-23T05:54:15Z"},"pay":null,"html_url":"https://alion.io/job/amd-sr-fellow-memory-phy-architect","json_url":"https://alion.io/job/amd-sr-fellow-memory-phy-architect.json","meta":{"generated_at":"2026-10-23T10:13:05Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":15565,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-24T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":93},"rest":"https://alion.io/mcp/rest/get_company?id=93"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Famd-sr-fellow-memory-phy-architect"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Famd-sr-fellow-memory-phy-architect"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Famd-sr-fellow-memory-phy-architect"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/amd-sr-fellow-memory-phy-architect\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Famd-sr-fellow-memory-phy-architect"}]}