{"id":3093259,"url":"https://alion.io/job/amd-sr-manager-dft","title":"Sr Manager - DFT","company":{"id":93,"name":"AMD","domain":"amd.com","url":"https://alion.io/company/amd","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Jibe","truth_index":{"grade":"B","score":80,"open_postings":157,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":15,"computed_at":"2026-10-22T06:10:10Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":19500,"max_usd":50000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":18},"experience_years_min":15,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Amazon S3","optional":false},{"name":"Perl","optional":true},{"name":"Python","optional":true},{"name":"Synopsys Design Compiler","optional":true},{"name":"Synopsys SpyGlass","optional":true},{"name":"SystemVerilog","optional":true},{"name":"Tessent","optional":true},{"name":"Verilog","optional":true}],"status":"live","first_seen_at":"2026-10-22T12:58:00Z","employer_posted_date":"2026-10-22","last_verified_at":"2026-10-22T23:33:01Z","board_verified":true,"closed_at":null,"days_open":0,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":0},"description":"ADVANCE YOUR CAREER. ADVANCE THE WORLD.\nAt AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.\nWhether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Join us and, together, we’ll advance your career.\nSenior Manager, DFT\nTHE ROLE:\nAs a Senior Manager - DFT Design within the S3 SoC DFT Team, the successful candidate will provide technical and people leadership for the DFT organization responsible for the architecture, design, integration, verification, and silicon enablement of advanced DFT solutions across complex SoCs.\nThe candidate will lead a team of DFT engineers and work closely with DFT Architecture, RTL Design, Verification, Physical Design, STA, Test, and Post-Silicon teams to drive robust and scalable DFT solutions across multiple programs.\nThis role requires a strong combination of deep DFT technical expertise, team leadership, execution ownership, and cross-functional collaboration.\nKEY RESPONSIBILITIES:\nLead and manage a team of DFT engineers responsible for end-to-end DFT design, integration, verification, and implementation.\nProvide technical leadership for complex DFT architectures including Scan, ATPG, MBIST, Boundary Scan/JTAG and related test methodologies.\nOwn DFT execution from architecture and requirements definition through RTL implementation, verification, physical implementation support, pattern generation, and silicon bring-up.\nPartner closely with DFT Architecture and IP/SoC Design teams to define requirements and drive successful DFT implementation across complex SoCs.\nDrive correct-by-construction DFT methodologies, design quality, verification completeness, and predictable execution.\nWork closely with RTL Design, Verification, Physical Design, STA, and Test Engineering teams to resolve complex design, timing, implementation, and testability challenges.\nLead technical reviews and provide guidance on DFT architecture, methodologies, implementation, verification, and debug.\nDrive execution planning, resource prioritization, risk identification, and timely closure of technical dependencies and program deliverables.\nDevelop and improve DFT methodologies, automation, flows, and infrastructure to improve engineering productivity and design quality.\nProvide hands-on technical guidance for complex ATPG, scan, MBIST, timing, simulation, and silicon-debug issues.\nBuild and develop engineering talent through mentoring, technical guidance, and capability development.\nCollaborate effectively with geographically distributed engineering teams and stakeholders.\nPREFERRED EXPERIENCE:\nExtensive experience in ASIC/SoC DFT architecture, design, integration, verification, and implementation.\nStrong experience leading end-to-end DFT execution for complex, high-performance SoCs.\nDemonstrated experience leading and mentoring DFT engineers and driving technical execution across multiple projects/programs.\nDeep understanding of Scan insertion, ATPG, compression, MBIST, Boundary Scan/JTAG, test modes and test architecture.\nStrong experience with industry-standard DFT and implementation tools such as Siemens Tessent, Synopsys Design Compiler and SpyGlass or equivalent tools.\nExperience defining and developing scalable DFT flows and methodologies.\nStrong knowledge of RTL development and integration using Verilog/SystemVerilog.\nExperience integrating multiple IPs and DFT structures into large and complex SoCs.\nGood understanding of synthesis, simulation, CDC, lint, RTL quality checks, and design verification methodologies.\nStrong understanding of Static Timing Analysis, DFT timing constraints and timing closure.\nExperience in Scan/ATPG pattern generation, test-flow development, debug, coverage analysis, and characterization.\nExcellent hands-on debugging skills with the ability to drive complex technical issues to closure.\nStrong scripting and automation experience using Perl, Python and TCL.\nUnderstanding of low-power design concepts including clock gating and power gating.\nExperience with post-silicon bring-up and silicon DFT/debug is highly desirable.\nStrong communication, stakeholder-management, and organizational skills with the ability to work effectively across global engineering teams.\nProven ability to balance technical depth, people leadership, program execution, and strategic priorities.\nACADEMIC CREDENTIALS:\nB.E./B.Tech./M.E./M.Tech. in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related discipline.\nTypically 15+ years of relevant semiconductor/SoC design experience, with significant experience in DFT and technical/team leadership.#LI-RR1\n\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.\nSenior Manager, DFT\nTHE ROLE:\nAs a Senior Manager - DFT Design within the S3 SoC DFT Team, the successful candidate will provide technical and people leadership for the DFT organization responsible for the architecture, design, integration, verification, and silicon enablement of advanced DFT solutions across complex SoCs.\nThe candidate will lead a team of DFT engineers and work closely with DFT Architecture, RTL Design, Verification, Physical Design, STA, Test, and Post-Silicon teams to drive robust and scalable DFT solutions across multiple programs.\nThis role requires a strong combination of deep DFT technical expertise, team leadership, execution ownership, and cross-functional collaboration.\nKEY RESPONSIBILITIES:\nLead and manage a team of DFT engineers responsible for end-to-end DFT design, integration, verification, and implementation.\nProvide technical leadership for complex DFT architectures including Scan, ATPG, MBIST, Boundary Scan/JTAG and related test methodologies.\nOwn DFT execution from architecture and requirements definition through RTL implementation, verification, physical implementation support, pattern generation, and silicon bring-up.\nPartner closely with DFT Architecture and IP/SoC Design teams to define requirements and drive successful DFT implementation across complex SoCs.\nDrive correct-by-construction DFT methodologies, design quality, verification completeness, and predictable execution.\nWork closely with RTL Design, Verification, Physical Design, STA, and Test Engineering teams to resolve complex design, timing, implementation, and testability challenges.\nLead technical reviews and provide guidance on DFT architecture, methodologies, implementation, verification, and debug.\nDrive execution planning, resource prioritization, risk identification, and timely closure of technical dependencies and program deliverables.\nDevelop and improve DFT methodologies, automation, flows, and infrastructure to improve engineering productivity and design quality.\nProvide hands-on technical guidance for complex ATPG, scan, MBIST, timing, simulation, and silicon-debug issues.\nBuild and develop engineering talent through mentoring, technical guidance, and capability development.\nCollaborate effectively with geographically distributed engineering teams and stakeholders.\nPREFERRED EXPERIENCE:\nExtensive experience in ASIC/SoC DFT architecture, design, integration, verification, and implementation.\nStrong experience leading end-to-end DFT execution for complex, high-performance SoCs.\nDemonstrated experience leading and mentoring DFT engineers and driving technical execution across multiple projects/programs.\nDeep understanding of Scan insertion, ATPG, compression, MBIST, Boundary Scan/JTAG, test modes and test architecture.\nStrong experience with industry-standard DFT and implementation tools such as Siemens Tessent, Synopsys Design Compiler and SpyGlass or equivalent tools.\nExperience defining and developing scalable DFT flows and methodologies.\nStrong knowledge of RTL development and integration using Verilog/SystemVerilog.\nExperience integrating multiple IPs and DFT structures into large and complex SoCs.\nGood understanding of synthesis, simulation, CDC, lint, RTL quality checks, and design verification methodologies.\nStrong understanding of Static Timing Analysis, DFT timing constraints and timing closure.\nExperience in Scan/ATPG pattern generation, test-flow development, debug, coverage analysis, and characterization.\nExcellent hands-on debugging skills with the ability to drive complex technical issues to closure.\nStrong scripting and automation experience using Perl, Python and TCL.\nUnderstanding of low-power design concepts including clock gating and power gating.\nExperience with post-silicon bring-up and silicon DFT/debug is highly desirable.\nStrong communication, stakeholder-management, and organizational skills with the ability to work effectively across global engineering teams.\nProven ability to balance technical depth, people leadership, program execution, and strategic priorities.\nACADEMIC CREDENTIALS:\nB.E./B.Tech./M.E./M.Tech. in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related discipline.\nTypically 15+ years of relevant semiconductor/SoC design experience, with significant experience in DFT and technical/team leadership.#LI-RR1\n\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. 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