{"id":2910133,"url":"https://alion.io/job/amd-sr-manager-rtl-design-manager","title":"Sr. Manager - RTL Design Manager","company":{"id":93,"name":"AMD","domain":"amd.com","url":"https://alion.io/company/amd","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Jibe","truth_index":{"grade":"B","score":80,"open_postings":160,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":20,"computed_at":"2026-10-23T05:54:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Markham, Canada"],"countries":["CA"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":73000,"max_usd":131000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":64},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Formal Verification","optional":true},{"name":"SystemVerilog","optional":true},{"name":"Verilog","optional":true}],"status":"live","first_seen_at":"2026-10-09T12:07:00Z","employer_posted_date":"2026-10-20","last_verified_at":"2026-10-23T13:34:26Z","board_verified":true,"closed_at":null,"days_open":14,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":14},"description":"ADVANCE YOUR CAREER. ADVANCE THE WORLD.\nAt AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.\nWhether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Join us and, together, we’ll advance your career.\n THE ROLE:\nWe are seeking a highly motivated Silicon RTL Design Manager to join the Security IP (SECIP) Design team. The team is responsible for the architecture, design, implementation, and verification of a broad portfolio of embedded microprocessor (MP) subsystems and hardware accelerators that enhance performance, functionality, security, and power efficiency across AMD System-on-Chip (SoC) products spanning client, server, graphics, and gaming platforms.\nIn this role, you will partner closely with IP architecture teams to define IP and subsystem functional specifications, establish and track key design goals, and drive design optimization initiatives. You will collaborate with RTL design, IP integration, power design and analysis, verification, and validation teams to deliver high-quality solutions that meet performance, power, area, and schedule targets.\nYou will also work with corporate design methodology teams, SoC organizations, and other IP design teams to develop and adopt both traditional and AI-assisted design methodologies and flows. Your expertise will play a critical role in enabling engineering teams to achieve ambitious design objectives across a diverse set of applications while maintaining the highest standards of quality, efficiency, and scalability. This role combines technical leadership, project execution, and people management responsibilities in a fast-paced and highly collaborative environment.\nTHE PERSON:\nWe are looking for a highly motivated engineering leader with a proven track record of technical excellence, ownership, execution, and team leadership. The ideal candidate is an innovative and analytical thinker who is passionate about solving complex engineering challenges, driving continuous improvement, and developing scalable solutions.\nThe successful candidate proactively identifies risks, resolves technical issues, and delivers results in a dynamic environment. They excel at mentoring and developing engineers, fostering collaboration across organizations, and building strong, high-performing teams. Strong communication, interpersonal, and organizational skills, combined with attention to detail and sound engineering judgment, are essential for success in this role.\nKEY RESPONSIBILITIES:\nDefine, develop, and maintain RTL-level IP and subsystem functional specifications, and align microarchitecture and design solutions with product requirements in collaboration with SoC, architecture, design, verification, and validation teams.\nEstablish, track, and drive key design metrics and targets by correlating design intent with implementation results and identifying optimization opportunities.\nLead and coordinate RTL design activities from specification through integration and project delivery.\nCollaborate with functional and implementation verification teams to debug and resolve design issues across simulation, formal, emulation, and post-silicon validation environments.\nWork with corporate methodology and SoC integration teams to adopt and develop traditional and AI-assisted methodologies for microarchitecture development, RTL design, structural analysis, and design validation.\nDrive the closure of RTL quality metrics, including lint, CDC, RDC, synthesis, low-power verification, and other implementation-related checks.\nCoordinate resolution of IP integration issues with SoC integration, SoC verification, firmware, and post-silicon validation teams.\nPartner with project managers, architects, and technical leads to ensure delivery of IP milestones while meeting schedule, quality, power, performance, and area objectives.\nMentor, coach, and develop engineers while fostering a culture of technical excellence, innovation, collaboration, and accountability.\nPREFERRED EXPERIENCE:\nPrevious experience managing IP or RTL design engineering teams.\nStrong expertise in Verilog/SystemVerilog and scripting-based development environments.\nDeep knowledge in one or more areas of RTL microarchitecture, digital design, implementation analysis, and industry-standard design methodologies.\nStrong understanding of microprocessor (MP) subsystem architectures, datapath design, and low-power design techniques.\nSolid understanding of industry-standard on-chip interconnect and interface protocols, including AMBA, AXI, and AHB.\nExperience with ASIC design and verification flows, including RTL simulation, linting, CDC/RDC analysis, synthesis, power-aware design and verification, formal verification, and debug methodologies.\nExperience correlating RTL design decisions to implementation metrics such as performance, power, area, timing, and overall design quality.\nDemonstrated ability to drive technical solutions and collaborate effectively across architecture, design, verification, implementation, methodology, and SoC organizations.\nProven ability to mentor and develop engineers at various career levels while positively influencing team culture and engagement.\nExperience leading complex cross-functional projects from concept through silicon bring-up is a strong asset.\nACADEMIC CREDENTIALS:\nBachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline.\nMaster's degree or Ph.D. preferred.\nLOCATION: MARKHAM, ON ( Consider Austin, TX)\n#LI-SL3\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.\nTHE ROLE:\nWe are seeking a highly motivated Silicon RTL Design Manager to join the Security IP (SECIP) Design team. The team is responsible for the architecture, design, implementation, and verification of a broad portfolio of embedded microprocessor (MP) subsystems and hardware accelerators that enhance performance, functionality, security, and power efficiency across AMD System-on-Chip (SoC) products spanning client, server, graphics, and gaming platforms.\nIn this role, you will partner closely with IP architecture teams to define IP and subsystem functional specifications, establish and track key design goals, and drive design optimization initiatives. You will collaborate with RTL design, IP integration, power design and analysis, verification, and validation teams to deliver high-quality solutions that meet performance, power, area, and schedule targets.\nYou will also work with corporate design methodology teams, SoC organizations, and other IP design teams to develop and adopt both traditional and AI-assisted design methodologies and flows. Your expertise will play a critical role in enabling engineering teams to achieve ambitious design objectives across a diverse set of applications while maintaining the highest standards of quality, efficiency, and scalability. This role combines technical leadership, project execution, and people management responsibilities in a fast-paced and highly collaborative environment.\nTHE PERSON:\nWe are looking for a highly motivated engineering leader with a proven track record of technical excellence, ownership, execution, and team leadership. The ideal candidate is an innovative and analytical thinker who is passionate about solving complex engineering challenges, driving continuous improvement, and developing scalable solutions.\nThe successful candidate proactively identifies risks, resolves technical issues, and delivers results in a dynamic environment. They excel at mentoring and developing engineers, fostering collaboration across organizations, and building strong, high-performing teams. Strong communication, interpersonal, and organizational skills, combined with attention to detail and sound engineering judgment, are essential for success in this role.\nKEY RESPONSIBILITIES:\nDefine, develop, and maintain RTL-level IP and subsystem functional specifications, and align microarchitecture and design solutions with product requirements in collaboration with SoC, architecture, design, verification, and validation teams.\nEstablish, track, and drive key design metrics and targets by correlating design intent with implementation results and identifying optimization opportunities.\nLead and coordinate RTL design activities from specification through integration and project delivery.\nCollaborate with functional and implementation verification teams to debug and resolve design issues across simulation, formal, emulation, and post-silicon validation environments.\nWork with corporate methodology and SoC integration teams to adopt and develop traditional and AI-assisted methodologies for microarchitecture development, RTL design, structural analysis, and design validation.\nDrive the closure of RTL quality metrics, including lint, CDC, RDC, synthesis, low-power verification, and other implementation-related checks.\nCoordinate resolution of IP integration issues with SoC integration, SoC verification, firmware, and post-silicon validation teams.\nPartner with project managers, architects, and technical leads to ensure delivery of IP milestones while meeting schedule, quality, power, performance, and area objectives.\nMentor, coach, and develop engineers while fostering a culture of technical excellence, innovation, collaboration, and accountability.\nPREFERRED EXPERIENCE:\nPrevious experience managing IP or RTL design engineering teams.\nStrong expertise in Verilog/SystemVerilog and scripting-based development environments.\nDeep knowledge in one or more areas of RTL microarchitecture, digital design, implementation analysis, and industry-standard design methodologies.\nStrong understanding of microprocessor (MP) subsystem architectures, datapath design, and low-power design techniques.\nSolid understanding of industry-standard on-chip interconnect and interface protocols, including AMBA, AXI, and AHB.\nExperience with ASIC design and verification flows, including RTL simulation, linting, CDC/RDC analysis, synthesis, power-aware design and verification, formal verification, and debug methodologies.\nExperience correlating RTL design decisions to implementation metrics such as performance, power, area, timing, and overall design quality.\nDemonstrated ability to drive technical solutions and collaborate effectively across architecture, design, verification, implementation, methodology, and SoC organizations.\nProven ability to mentor and develop engineers at various career levels while positively influencing team culture and engagement.\nExperience leading complex cross-functional projects from concept through silicon bring-up is a strong asset.\nACADEMIC CREDENTIALS:\nBachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline.\nMaster's degree or Ph.D. preferred...","description_format":"text","description_chars":13011,"description_truncated":true,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Computer Components","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-10-20T09:19:33Z"}],"visa":[],"liveness":{"score":53,"band":"ok","label":"Likely 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