{"id":3170341,"url":"https://alion.io/job/amd-sr-physical-design-engineer","title":"Sr Physical Design Engineer","company":{"id":93,"name":"AMD","domain":"amd.com","url":"https://alion.io/company/amd","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Jibe","truth_index":{"grade":"B","score":80,"open_postings":160,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":20,"computed_at":"2026-10-23T05:54:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Santa Clara, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":142000,"max_usd":259000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":1396},"experience_years_min":null,"visa_sponsorship":true,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Verilog","optional":true}],"status":"live","first_seen_at":"2026-10-23T18:01:00Z","employer_posted_date":"2026-10-23","last_verified_at":"2026-10-23T22:32:24Z","board_verified":true,"closed_at":null,"days_open":0,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":0},"description":"ADVANCE YOUR CAREER. ADVANCE THE WORLD.\nAt AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.\nWhether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Join us and, together, we’ll advance your career.\nTHE ROLE:\nJoin a team developing high-performance, multi-gigabit SerDes PHY and advanced IP designs. In this Physical Design Engineering role, you will contribute across the full RTL-to-GDS implementation lifecycle, working on challenging designs where timing, power, area, and physical quality are critical.\nYou will collaborate with geographically distributed engineering teams and gain exposure to synthesis, floorplanning, timing-driven place and route, clock tree synthesis, physical verification, and final sign off. This is an opportunity to influence both individual designs and the methodologies and automated flows used to deliver complex IP efficiently and with high quality.\nTHE PERSON:\nThe successful candidate is a collaborative and technically curious engineer who enjoys solving complex physical design challenges. You communicate technical concepts clearly, work effectively with colleagues across different disciplines and locations, and can prioritize work across multiple projects.\nYou bring a thoughtful, analytical approach to problem solving and are comfortable balancing timing, power, area, quality, and schedule considerations. You are also interested in improving design methodologies and identifying opportunities to make engineering flows more efficient and scalable.\nKEY RESPONSIBILITIES:\nDrive physical implementation of high-performance RTL blocks through synthesis, floorplanning, timing-driven place and route, and signoff.\nDevelop and apply automated design flows for clock tree synthesis, clock and power gating, buffer/repeater insertion, scan stitching, and related implementation activities.\nAnalyze and optimize designs to achieve timing, power, area, physical, and electrical quality targets.\nSupport floorplanning, design methodology development, and integration of complex IP.\nPerform and support logic equivalence, timing, physical, and electrical quality checks.\nTroubleshoot implementation and timing challenges and collaboration with design teams to drive issues to closure.\nIdentify opportunities to improve automation, design methodology, quality, and overall design cycle time.\nSupport final signoff and delivery of large, high-performance IP blocks.\nBuild familiarity with the team's design environment and methodologies early in the role, progressing toward independent ownership of physical design blocks and optimization activities.\nPREFERRED EXPERIENCE:\nExperience taking digital designs through the RTL-to-GDS physical design flow.\nExperience with high-speed multi-gigabit SerDes PHY designs or other high-performance IP designs is preferred.\nExperience with automated logic synthesis and timing-driven place and route for high-speed datapath and control logic.\nVerilog experience is preferred.\nExperience with clock tree synthesis, clock and power gating, buffer/repeater insertion, scan stitching, and design optimization.\nKnowledge of timing, power, and area optimization techniques.\nUnderstanding of digital circuit techniques, logic optimization, and implementation approaches for high-speed, low-power applications.\nExperience with floorplanning, IP integration, logic equivalence checking, physical verification, timing analysis, electrical quality checks, and final signoff.\nExperience with industry EDA tools for logic synthesis, place and route, static timing analysis, and physical/electrical design checks.\nFamiliarity with schematic, layout, circuit simulation, or logic simulation tools is desired.\nExperience developing, automating, or improving physical design methodologies and flows is preferred.\nACADEMIC CREDENTIALS:\nBachelor's or master’s degree in electrical engineering, Computer Science, or a related technical discipline is preferred.\nRelevant technical education or equivalent practical experience in semiconductor or physical design engineering is also valued.\nAcademic or professional exposure to high-speed SerDes PHY, high-performance digital IP, or related semiconductor design is desired.\nThis role is not eligible for visa sponsorship.\n#LI-DP1\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.\nTHE ROLE:\nJoin a team developing high-performance, multi-gigabit SerDes PHY and advanced IP designs. In this Physical Design Engineering role, you will contribute across the full RTL-to-GDS implementation lifecycle, working on challenging designs where timing, power, area, and physical quality are critical.\nYou will collaborate with geographically distributed engineering teams and gain exposure to synthesis, floorplanning, timing-driven place and route, clock tree synthesis, physical verification, and final sign off. This is an opportunity to influence both individual designs and the methodologies and automated flows used to deliver complex IP efficiently and with high quality.\nTHE PERSON:\nThe successful candidate is a collaborative and technically curious engineer who enjoys solving complex physical design challenges. You communicate technical concepts clearly, work effectively with colleagues across different disciplines and locations, and can prioritize work across multiple projects.\nYou bring a thoughtful, analytical approach to problem solving and are comfortable balancing timing, power, area, quality, and schedule considerations. You are also interested in improving design methodologies and identifying opportunities to make engineering flows more efficient and scalable.\nKEY RESPONSIBILITIES:\nDrive physical implementation of high-performance RTL blocks through synthesis, floorplanning, timing-driven place and route, and signoff.\nDevelop and apply automated design flows for clock tree synthesis, clock and power gating, buffer/repeater insertion, scan stitching, and related implementation activities.\nAnalyze and optimize designs to achieve timing, power, area, physical, and electrical quality targets.\nSupport floorplanning, design methodology development, and integration of complex IP.\nPerform and support logic equivalence, timing, physical, and electrical quality checks.\nTroubleshoot implementation and timing challenges and collaboration with design teams to drive issues to closure.\nIdentify opportunities to improve automation, design methodology, quality, and overall design cycle time.\nSupport final signoff and delivery of large, high-performance IP blocks.\nBuild familiarity with the team's design environment and methodologies early in the role, progressing toward independent ownership of physical design blocks and optimization activities.\nPREFERRED EXPERIENCE:\nExperience taking digital designs through the RTL-to-GDS physical design flow.\nExperience with high-speed multi-gigabit SerDes PHY designs or other high-performance IP designs is preferred.\nExperience with automated logic synthesis and timing-driven place and route for high-speed datapath and control logic.\nVerilog experience is preferred.\nExperience with clock tree synthesis, clock and power gating, buffer/repeater insertion, scan stitching, and design optimization.\nKnowledge of timing, power, and area optimization techniques.\nUnderstanding of digital circuit techniques, logic optimization, and implementation approaches for high-speed, low-power applications.\nExperience with floorplanning, IP integration, logic equivalence checking, physical verification, timing analysis, electrical quality checks, and final signoff.\nExperience with industry EDA tools for logic synthesis, place and route, static timing analysis, and physical/electrical design checks.\nFamiliarity with schematic, layout, circuit simulation, or logic simulation tools is desired.\nExperience developing, automating, or improving physical design methodologies and flows is preferred.\nACADEMIC CREDENTIALS:\nBachelor's or master’s degree in electrical engineering, Computer Science, or a related technical discipline is preferred.\nRelevant technical education or equivalent practical experience in semiconductor or physical design engineering is also valued.\nAcademic or professional exposure to high-speed SerDes PHY, high-performance digital IP, or related semiconductor design is desired.\nThis role is not eligible for visa sponsorship.\n#LI-DP1\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.","description_format":"text","description_chars":10526,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Computer Components","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-10-23T18:20:04Z"}],"visa":[],"liveness":{"score":86,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.86,"p_room":1,"age_days":0,"expected_fill_days":20,"reasons":["conf:2","win:early","comp:brand"],"computed_at":"2026-10-24T01:12:59Z"},"pay":null,"html_url":"https://alion.io/job/amd-sr-physical-design-engineer","json_url":"https://alion.io/job/amd-sr-physical-design-engineer.json","meta":{"generated_at":"2026-10-24T01:12:59Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":1982,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-25T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":93},"rest":"https://alion.io/mcp/rest/get_company?id=93"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Famd-sr-physical-design-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Famd-sr-physical-design-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Famd-sr-physical-design-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/amd-sr-physical-design-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Famd-sr-physical-design-engineer"}]}