{"id":3842521,"url":"https://alion.io/job/amd-sr-silicon-design-engineer-hardware-software-co-design","title":"Sr. Silicon Design Engineer: Hardware-Software Co-Design","company":{"id":93,"name":"AMD","domain":"amd.com","url":"https://alion.io/company/amd","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Jibe","truth_index":{"grade":"A","score":97,"open_postings":17,"ghost_share":0,"stale_share":0.118,"repost_share":0,"time_to_fill_p50_days":49,"computed_at":"2026-11-09T06:03:00Z"}},"role":"Backend","role_family":"Backend","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bellevue, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":true,"relocation_package":false,"has_equity":false,"technologies":[{"name":"IREE","optional":false},{"name":"Linux","optional":false},{"name":"PyTorch","optional":false},{"name":"ROCm","optional":false},{"name":"Triton","optional":false},{"name":"C++","optional":true},{"name":"CUDA","optional":true},{"name":"HPC","optional":true},{"name":"KV Cache","optional":true},{"name":"LLVM","optional":true},{"name":"Mixture of Experts","optional":true},{"name":"MLIR","optional":true},{"name":"Python","optional":true},{"name":"Quantization","optional":true}],"status":"live","first_seen_at":"2026-11-05T17:42:00Z","employer_posted_date":"2026-11-05","last_verified_at":"2026-11-06T09:08:37Z","board_verified":false,"closed_at":null,"days_open":4,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":4},"description":"ADVANCE YOUR CAREER. ADVANCE THE WORLD.\nAt AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.\nWhether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Join us and, together, we’ll advance your career.\nTHE ROLE:\nThe AMD AI Group is looking for a Senior Silicon Design Engineer to co-design the hardware-software interface for AMD Instinct™ GPUs. You will work with hardware architects to model and evaluate how GPU microarchitecture, AI frameworks, and the ROCm™ software stack interact, using that analysis to drive improvements in both performance and energy efficiency across the AI compute stack.\nTHE PERSON:\nYou have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc. You are highly adept at collaboration among top-thinkers and engineers alike, ready to help elevate the knowledge and skills of the team around you.\nKEY RESPONSIBILITIES:\nYour day-to-day: build performance and power models that connect architectural decisions to real workload behavior. Evaluate proposed hardware features and software API designs against AI training and inference targets. Write and optimize GPU kernels and compiler passes that exploit microarchitectural characteristics. Work across the stack: the Linux kernel DRM/GEM layer, the ROCm™ runtime, the IREE compiler, and AI frameworks and DSLs like PyTorch and Triton.\nHardware-Software Co-Design & Performance\nLeverage detailed performance models that bridge GPU microarchitecture and software execution, including instruction execution, memory hierarchy behavior, networking, and compute-memory overlap. You will use those models to drive both software optimization and hardware design feedback.\nAnalyze and characterize AI workloads (training and inference) against AMD Instinct™ microarchitecture to identify performance bottlenecks, inform silicon roadmap decisions, and validate that architectural features deliver expected real-world speedups. \nCollaborate directly with AMD GPU hardware and firmware teams to evaluate proposed hardware features, providing software-grounded analysis of how changes to the memory subsystem, cache coherence protocols, or execution units affect workloads that matter. \nOwn the feedback loop between workload characterization and hardware design: build the methodology, tooling, and benchmarks that make this loop fast and evidence-driven across Instinct generations.\nCompiler & Runtime Infrastructure\nContribute to the IREE compiler and ROCm™ stack, with focus on backend optimizations, runtime API extensions, and firmware command packet design that target AMD GPU microarchitecture.\nDesign and optimize compute runtime paths including AI framework dispatch, data movement, and pipelining, minimizing overhead and maximizing hardware utilization for latency-sensitive and throughput-critical workloads.\nWork at the Linux kernel level on GPU compute infrastructure to improve asynchronous execution and reduce latency.\nCross-Cutting\nContribute to the open ROCm™ ecosystem, across the stack, in ways that raises the bar for the entire AMD AI developer experience.\nDevelop reproducible benchmarks and performance regression infrastructure that keeps the full stack honest across compiler, runtime, and driver changes.\nRepresent the software perspective in silicon architecture reviews and represent hardware realities to the software and framework teams. Be the person who holds both models in their head at once.\nCollaborate with AMD architecture teams to provide software feedback on next-generation Instinct™ GPU designs for both training and inference workloads.\n\nPREFERRED EXPERIENCE:\nIndustry experience working at the boundary of GPU compute hardware and AI systems software.\nStrong computer architecture foundation: memory consistency and coherence models, GPU microarchitecture, pipelining, and the ability to reason precisely about what hardware is doing on a given workload.\nDemonstrated performance modeling skills and the ability to build analytical or simulation-based models that predict real hardware behavior and use them to make engineering decisions.\nProficiency in C and C++ in system-level contexts, and Python for tooling, analysis, and framework-level work.\nExperience with GPU programming via CUDA and/or HIP, including writing and optimizing compute kernels beyond library calls.\nFamiliarity with Linux kernel internals relevant to GPU compute: DRM/GEM subsystem, kernel-mode driver interfaces, memory management, and userspace-kernel interaction patterns.\nExperience with compute runtimes and the full dispatch path from framework-level operations to GPU execution.\nExperience with AI framework internals including PyTorch dispatcher, Triton compiler, or equivalent depth in how frameworks lower operations to hardware.\nDirect experience with AMD Instinct GPU architectures (MI300X, MI350X, MI355X) and the ROCm™ stack.\nWorking knowledge of compiler infrastructure such as LLVM/MLIR-based flows, backend code generation, or related optimization passes. Experience with IREE is a strong plus.\nFamiliarity with modern AI model architecture: quantization techniques, KV cache, attention mechanisms and their variants, mixture-of-experts routing, or emerging state space models and an understanding of what these architectures demand from hardware.\nExperience with performance analysis tools for GPUs like profilers, trace viewers, hardware counters and building custom tooling on top of them.\nPublications or patents in HPC, ML systems, or GPU kernel optimization.\nPREFERRED ACADEMIC CREDENTIALS:\nBachelors or Mastersdegree in Computer Science, Computer Engineering, or a related field.\nLOCATION: San Jose, CA\nThis role is not eligible for visa sponsorship.\n#LI-G11\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.\nTHE ROLE:\nThe AMD AI Group is looking for a Senior Silicon Design Engineer to co-design the hardware-software interface for AMD Instinct™ GPUs. You will work with hardware architects to model and evaluate how GPU microarchitecture, AI frameworks, and the ROCm™ software stack interact, using that analysis to drive improvements in both performance and energy efficiency across the AI compute stack.\nTHE PERSON:\nYou have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc. You are highly adept at collaboration among top-thinkers and engineers alike, ready to help elevate the knowledge and skills of the team around you.\nKEY RESPONSIBILITIES:\nYour day-to-day: build performance and power models that connect architectural decisions to real workload behavior. Evaluate proposed hardware features and software API designs against AI training and inference targets. Write and optimize GPU kernels and compiler passes that exploit microarchitectural characteristics. Work across the stack: the Linux kernel DRM/GEM layer, the ROCm™ runtime, the IREE compiler, and AI frameworks and DSLs like PyTorch and Triton.\nHardware-Software Co-Design & Performance\nLeverage detailed performance models that bridge GPU microarchitecture and software execution, including instruction execution, memory hierarchy behavior, networking, and compute-memory overlap. You will use those models to drive both software optimization and hardware design feedback.\nAnalyze and characterize AI workloads (training and inference) against AMD Instinct™ microarchitecture to identify performance bottlenecks, inform silicon roadmap decisions, and validate that architectural features deliver expected real-world speedups. \nCollaborate directly with AMD GPU hardware and firmware teams to evaluate proposed hardware features, providing software-grounded analysis of how changes to the memory subsystem, cache coherence protocols, or execution units affect workloads that matter. \nOwn the feedback loop between workload characterization and hardware design: build the methodology, tooling, and benchmarks that make this loop fast and evidence-driven across Instinct generations.\nCompiler & Runtime Infrastructure\nContribute to the IREE compiler and ROCm™ stack, with focus on backend optimizations, runtime API extensions, and firmware command packet design that target AMD GPU microarchitecture.\nDesign and optimize compute runtime paths including AI framework dispatch, data movement, and pipelining, minimizing overhead and maximizing hardware utilization for latency-sensitive and throughput-critical workloads.\nWork at the Linux kernel level on GPU compute infrastructure to improve asynchronous execution and reduce latency.\nCross-Cutting\nContribute to the open ROCm™ ecosystem, across the stack, in ways that raises the bar for the entire AMD AI developer experience.\nDevelop reproducible benchmarks and performance regression infrastructure that keeps the full stack honest across compiler, runtime, and driver changes.\nRepresent the software perspective in silicon architecture reviews and represent hardware realities to the software and framework teams. Be the person who holds both models in their head at once.\nCollaborate with AMD architecture teams to provide software feedback on next-generation Instinct™ GPU designs for both training and inference workloads.\n\nPREFERRED EXPERIENCE:\nIndustry experience working at the boundary of GPU compute hardware and AI systems software.\nStrong computer architecture foundation: memory consistency and coherence models, GPU microarchitecture, pipelining, and the ability to reason precisely about what hardware is doing on a given workload.\nDemonstrated performance modeling skills and the ability to build analytical or simulation-based models that predict real hardware behavior and use them to make engineering decisions.\nProficiency in C and C++ in system-level contexts, and Python for tooling, analysis, and framework-level work.\nExperience with GPU programming via CUDA and/or HIP, including writing and optimizing compute kernels beyond library calls.\nFamiliarity with Linux kernel internals relevant to GPU compute: DRM/GEM subsystem, kernel-mode driver interfaces, memory management, and userspace-kernel interaction patterns.\nExperience with compute runtimes and the full dispatch path from framework-level operations to GPU execution.\nExperience with AI framework internals including PyTorch dispatcher, Triton compiler, or equivalent depth in how frameworks lower operations to hardware.\nDirect experience with AMD Instinct GPU architectures (MI300X, MI350X, MI355X) and the ROCm™ stack.\nWorking knowledge of compiler infrastructure such as LLVM/MLIR-based flows, backend code generation, or related optimization passes. Experience with IREE is a strong plus.\nFamiliarity with modern AI model architecture: qu...","description_format":"text","description_chars":13578,"description_truncated":true,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":true},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Computer Components","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-11-05T23:29:06Z"}],"visa":[],"liveness":{"score":81,"band":"hot","label":"Hiring now","p_open":0.9,"p_active":0.903,"p_room":1,"age_days":3,"expected_fill_days":49,"reasons":["conf:68","velocity","win:early","comp:brand"],"computed_at":"2026-11-09T06:03:00Z"},"pay":null,"html_url":"https://alion.io/job/amd-sr-silicon-design-engineer-hardware-software-co-design","json_url":"https://alion.io/job/amd-sr-silicon-design-engineer-hardware-software-co-design.json","meta":{"generated_at":"2026-11-09T18:23:12Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":2946,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-10T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.1,"usd":0.01,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":93},"rest":"https://alion.io/mcp/rest/get_company?id=93"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Famd-sr-silicon-design-engineer-hardware-software-co-design"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":2,"usd":0.2},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Famd-sr-silicon-design-engineer-hardware-software-co-design"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.1,"usd":0.01},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Famd-sr-silicon-design-engineer-hardware-software-co-design"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/amd-sr-silicon-design-engineer-hardware-software-co-design\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Famd-sr-silicon-design-engineer-hardware-software-co-design"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":3842521}},{"tool":"search_jobs","arguments":{"company":"amd.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":3842521},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. Docs: https://alion.io/developers"}}