{"id":2911359,"url":"https://alion.io/job/amd-sr-staff-design-verification-engineer","title":"Sr. Staff Design Verification Engineer","company":{"id":93,"name":"AMD","domain":"amd.com","url":"https://alion.io/company/amd","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Jibe","truth_index":{"grade":"A","score":95,"open_postings":10,"ghost_share":0,"stale_share":0.2,"repost_share":0,"time_to_fill_p50_days":42,"computed_at":"2026-11-04T06:34:25Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bellevue, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":176000,"max_usd":324000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":563},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false},{"name":"Synopsys PrimeTime","optional":true},{"name":"Synopsys TestMAX","optional":true}],"status":"closed","first_seen_at":"2026-09-04T01:24:00Z","employer_posted_date":"2026-11-03","last_verified_at":"2026-11-04T01:47:01Z","board_verified":false,"closed_at":"2026-11-04T01:47:01Z","days_open":61,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":61},"description":"ADVANCE YOUR CAREER. ADVANCE THE WORLD.\nAt AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.\nWhether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Join us and, together, we’ll advance your career.\nTHE ROLE:\nAs a key member of AMD’s FPGA Product and Platform development team, you will have various responsibilities in the technical execution of Adaptive & Embedded Computing Group (AECG) device programs from definition to productization. You will leverage modern RTL design methodologies, advanced EDA tools, and AI-driven automation in supporting IP development for Silicon implementation and first-time-right SW solution.\nTHE PERSON:\n You are passionate about HW architecture, Digital design, and building cutting-edge silicon. As a strong problem solver and analytical thinker, you bring collaboration, communication, and adaptability to cross-functional teams spanning multiple time zones.\nKEY RESPONSIBILITIES:\nParticipate in all stages of the design flow, from RTL development through GDS implementation.\nDesign and implement RTL for complex digital and mixed-signal blocks using Verilog and System Verilog.\nSupport physical design activities, including synthesis, DFT implementation, place-and-route, and Static Timing Analysis (STA).\nCollaborate closely with Functional Verification teams to support block-level verification using constrained-random and directed test environments based on System Verilog and UVM.\nUtilize scripting languages such as Perl, Tcl, Shell, and Python to maintain existing design automation flows and develop new tools supporting various aspects of design implementation.\nPartner with cross-functional teams across multiple engineering disciplines and geographic locations.\nCommunicate regularly with global project teams to resolve technical issues and ensure project milestones and objectives are achieved.\nPREFERRED EXPERIENCE:\nStrong understanding of the complete ASIC/SoC development flow, from RTL architecture through physical implementation and silicon bring-up.\nStrong RTL design and integration experience using Verilog and SystemVerilog.\nExperience working with high-speed interfaces and complex IPs such as HBM, Die-to-Die (D2D), SerDes, PCIe, and memory subsystems.\nDeep understanding of VLSI design principles, Design Automation methodologies, and IC development processes.\nWorking knowledge of physical design concepts including floorplanning, synthesis, place-and-route, timing closure, and Static Timing Analysis (STA).\nHands-on experience with industry-standard EDA tools such as Synopsys DFT Compiler, TestMAX, PrimeTime, VCS, and Cadence tool suites.\nExperience with UVM/OVM verification methodologies, testbench development, BFMs, simulation environments, and debug workflows.\nProven experience implementing DFT solutions for large-scale SoCs, including scan, compression, MBIST, LBIST, boundary scan, and related test technologies.\nFamiliarity with FPGA architectures and prototyping methodologies is a plus.\nStrong scripting and automation skills using Perl, Tcl, Shell, Python, or similar languages.\nDemonstrated ability to independently drive technical initiatives and solve complex engineering challenges.\nExcellent written and verbal communication skills, with the ability to effectively collaborate across geographically distributed teams.\nProven ability to mentor engineers and contribute to technical leadership within an organization.\nACADEMIC CREDENTIALS:\nBachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.\nLOCATION:\nSan Jose, CA\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.\nTHE ROLE:\nAs a key member of AMD’s FPGA Product and Platform development team, you will have various responsibilities in the technical execution of Adaptive & Embedded Computing Group (AECG) device programs from definition to productization. You will leverage modern RTL design methodologies, advanced EDA tools, and AI-driven automation in supporting IP development for Silicon implementation and first-time-right SW solution.\nTHE PERSON:\n You are passionate about HW architecture, Digital design, and building cutting-edge silicon. As a strong problem solver and analytical thinker, you bring collaboration, communication, and adaptability to cross-functional teams spanning multiple time zones.\nKEY RESPONSIBILITIES:\nParticipate in all stages of the design flow, from RTL development through GDS implementation.\nDesign and implement RTL for complex digital and mixed-signal blocks using Verilog and System Verilog.\nSupport physical design activities, including synthesis, DFT implementation, place-and-route, and Static Timing Analysis (STA).\nCollaborate closely with Functional Verification teams to support block-level verification using constrained-random and directed test environments based on System Verilog and UVM.\nUtilize scripting languages such as Perl, Tcl, Shell, and Python to maintain existing design automation flows and develop new tools supporting various aspects of design implementation.\nPartner with cross-functional teams across multiple engineering disciplines and geographic locations.\nCommunicate regularly with global project teams to resolve technical issues and ensure project milestones and objectives are achieved.\nPREFERRED EXPERIENCE:\nStrong understanding of the complete ASIC/SoC development flow, from RTL architecture through physical implementation and silicon bring-up.\nStrong RTL design and integration experience using Verilog and SystemVerilog.\nExperience working with high-speed interfaces and complex IPs such as HBM, Die-to-Die (D2D), SerDes, PCIe, and memory subsystems.\nDeep understanding of VLSI design principles, Design Automation methodologies, and IC development processes.\nWorking knowledge of physical design concepts including floorplanning, synthesis, place-and-route, timing closure, and Static Timing Analysis (STA).\nHands-on experience with industry-standard EDA tools such as Synopsys DFT Compiler, TestMAX, PrimeTime, VCS, and Cadence tool suites.\nExperience with UVM/OVM verification methodologies, testbench development, BFMs, simulation environments, and debug workflows.\nProven experience implementing DFT solutions for large-scale SoCs, including scan, compression, MBIST, LBIST, boundary scan, and related test technologies.\nFamiliarity with FPGA architectures and prototyping methodologies is a plus.\nStrong scripting and automation skills using Perl, Tcl, Shell, Python, or similar languages.\nDemonstrated ability to independently drive technical initiatives and solve complex engineering challenges.\nExcellent written and verbal communication skills, with the ability to effectively collaborate across geographically distributed teams.\nProven ability to mentor engineers and contribute to technical leadership within an organization.\nACADEMIC CREDENTIALS:\nBachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.\nLOCATION:\nSan Jose, CA\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.","description_format":"text","description_chars":9158,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Computer Components","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-10-20T09:36:36Z"},{"event":"close","at":"2026-10-31T13:38:47Z"},{"event":"reopen","at":"2026-10-31T17:13:40Z"},{"event":"close","at":"2026-11-02T16:06:30Z"},{"event":"reopen","at":"2026-11-03T02:35:02Z"},{"event":"close","at":"2026-11-04T01:47:01Z"}],"visa":[],"liveness":null,"pay":null,"html_url":"https://alion.io/job/amd-sr-staff-design-verification-engineer","json_url":"https://alion.io/job/amd-sr-staff-design-verification-engineer.json","meta":{"generated_at":"2026-11-04T13:25:16Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":20271,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-05T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":93},"rest":"https://alion.io/mcp/rest/get_company?id=93"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Famd-sr-staff-design-verification-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Famd-sr-staff-design-verification-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Famd-sr-staff-design-verification-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/amd-sr-staff-design-verification-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Famd-sr-staff-design-verification-engineer"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":2911359}},{"tool":"search_jobs","arguments":{"company":"amd.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":2911359},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. Docs: https://alion.io/developers"}}