{"id":2944640,"url":"https://alion.io/job/amd-sr-staff-physical-design-engineer","title":"Sr. Staff Physical Design Engineer","company":{"id":93,"name":"AMD","domain":"amd.com","url":"https://alion.io/company/amd","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Jibe","truth_index":{"grade":"B","score":75,"open_postings":163,"ghost_share":0,"stale_share":0.994,"repost_share":0,"time_to_fill_p50_days":28,"computed_at":"2026-10-24T06:02:35Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Vancouver, Canada"],"countries":["CA"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":102000,"max_usd":175000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":16},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Ansys RedHawk","optional":true},{"name":"Cadence Innovus","optional":true},{"name":"Python","optional":true},{"name":"Synopsys Fusion Compiler","optional":true},{"name":"Synopsys PrimeTime","optional":true},{"name":"Synopsys StarRC","optional":true}],"status":"live","first_seen_at":"2026-10-20T15:10:00Z","employer_posted_date":"2026-10-20","last_verified_at":"2026-10-24T15:03:24Z","board_verified":true,"closed_at":null,"days_open":4,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":4},"description":"ADVANCE YOUR CAREER. ADVANCE THE WORLD.\nAt AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.\nWhether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Join us and, together, we’ll advance your career.\n THE ROLE:\nJoin an experienced physical design team working on AMD graphics IP for next-generation AI data center chips. In this role, you will own and drive complex physical design work for multi-million-gate blocks, delivering designs against challenging performance, power, and area targets using advanced process technologies. You will work closely with RTL design and other engineering partners throughout the project lifecycle, from floorplanning, synthesis, and placement through clock tree synthesis, routing, timing closure, extraction, physical verification, and final signoff. The role also provides opportunities to lead technical execution, establish design methodologies, improve automated design flows, and mentor other engineers.\nTHE PERSON:\nYou are a collaborative technical leader who brings strong analytical thinking, clear communication, and attention to detail to complex physical design challenges. You work effectively with RTL and physical design teams to solve problems, navigate technical tradeoffs, and keep designs moving toward closure. You take ownership of execution, communicate issues and priorities clearly across geographically distributed teams, and are comfortable providing technical guidance and mentoring to other engineers. You can balance multiple priorities while keeping the team focused on successful project delivery.\n\nKEY RESPONSIBILITIES:\nOwn the physical design of complex, multi-million-gate graphics IP blocks and drive designs toward required performance, power, and area targets.\nPartner with RTL design teams to identify frequency bottlenecks and address logic-level and timing issues early in the project lifecycle.\nDrive floorplanning, power planning, synthesis, placement, clock tree synthesis, routing, extraction, timing closure, and physical verification.\nPerform and support DRC/LVS verification, crosstalk analysis, and EM/IR analysis through final design signoff.\nEstablish and improve physical design methodologies for large IP delivery, including IP integration and design-quality checks.\nDrive design optimization for timing, power, area, and design-cycle efficiency.\nDevelop and enhance scripts and automated design flows to improve physical design execution.\nProvide technical leadership and mentoring to engineers throughout design closure.\nCollaborate across geographically distributed engineering teams to deliver projects against technical requirements.\nPREFERRED EXPERIENCE:\nStrong experience in physical design for high-performance semiconductor designs, including timing closure and physical signoff.\nExperience with synthesis and timing-driven place and route of RTL blocks for high-speed datapath and control-logic applications.\nExperience with floorplanning, clock tree synthesis, clock and power gating, scan stitching, routing, extraction, and physical verification.\nExperience with physical design and signoff tools such as Synopsys ICC2, ICC, Fusion Compiler, PrimeTime and StarRC; Mentor Graphics Calibre; Apache RedHawk; and Cadence Innovus and Genus.\nExperience establishing design methodologies, integrating IP, performing logic-equivalence checks, and validating physical, timing, and electrical quality for large IP delivery.\nExperience with advanced process technologies, including N2P or below.\nProficiency with Python and TCL for design-flow development and automation.\nExperience leading engineers through design closure and providing technical mentorship.\nFamiliarity with RTL design, logic-level optimization, and computer organization/architecture.\nExperience applying or developing AI techniques for performance, power, and area optimization is desirable.\nACADEMIC CREDENTIALS:\nBachelors or Masters in Electronics/Electrical Engineering preferred.\nLOCATIONS:\nVancouver, BC or Markham, ON\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.\nTHE ROLE:\nJoin an experienced physical design team working on AMD graphics IP for next-generation AI data center chips. In this role, you will own and drive complex physical design work for multi-million-gate blocks, delivering designs against challenging performance, power, and area targets using advanced process technologies. You will work closely with RTL design and other engineering partners throughout the project lifecycle, from floorplanning, synthesis, and placement through clock tree synthesis, routing, timing closure, extraction, physical verification, and final signoff. The role also provides opportunities to lead technical execution, establish design methodologies, improve automated design flows, and mentor other engineers.\nTHE PERSON:\nYou are a collaborative technical leader who brings strong analytical thinking, clear communication, and attention to detail to complex physical design challenges. You work effectively with RTL and physical design teams to solve problems, navigate technical tradeoffs, and keep designs moving toward closure. You take ownership of execution, communicate issues and priorities clearly across geographically distributed teams, and are comfortable providing technical guidance and mentoring to other engineers. You can balance multiple priorities while keeping the team focused on successful project delivery.\n\nKEY RESPONSIBILITIES:\nOwn the physical design of complex, multi-million-gate graphics IP blocks and drive designs toward required performance, power, and area targets.\nPartner with RTL design teams to identify frequency bottlenecks and address logic-level and timing issues early in the project lifecycle.\nDrive floorplanning, power planning, synthesis, placement, clock tree synthesis, routing, extraction, timing closure, and physical verification.\nPerform and support DRC/LVS verification, crosstalk analysis, and EM/IR analysis through final design signoff.\nEstablish and improve physical design methodologies for large IP delivery, including IP integration and design-quality checks.\nDrive design optimization for timing, power, area, and design-cycle efficiency.\nDevelop and enhance scripts and automated design flows to improve physical design execution.\nProvide technical leadership and mentoring to engineers throughout design closure.\nCollaborate across geographically distributed engineering teams to deliver projects against technical requirements.\nPREFERRED EXPERIENCE:\nStrong experience in physical design for high-performance semiconductor designs, including timing closure and physical signoff.\nExperience with synthesis and timing-driven place and route of RTL blocks for high-speed datapath and control-logic applications.\nExperience with floorplanning, clock tree synthesis, clock and power gating, scan stitching, routing, extraction, and physical verification.\nExperience with physical design and signoff tools such as Synopsys ICC2, ICC, Fusion Compiler, PrimeTime and StarRC; Mentor Graphics Calibre; Apache RedHawk; and Cadence Innovus and Genus.\nExperience establishing design methodologies, integrating IP, performing logic-equivalence checks, and validating physical, timing, and electrical quality for large IP delivery.\nExperience with advanced process technologies, including N2P or below.\nProficiency with Python and TCL for design-flow development and automation.\nExperience leading engineers through design closure and providing technical mentorship.\nFamiliarity with RTL design, logic-level optimization, and computer organization/architecture.\nExperience applying or developing AI techniques for performance, power, and area optimization is desirable.\nACADEMIC CREDENTIALS:\nBachelors or Masters in Electronics/Electrical Engineering preferred.\nLOCATIONS:\nVancouver, BC or Markham, ON\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. 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