{"id":2910565,"url":"https://alion.io/job/amd-sr-staffstaff-silicon-design-engineer-pcie","title":"Sr. STAFF/STAFF SILICON DESIGN ENGINEER (PCIe)","company":{"id":93,"name":"AMD","domain":"amd.com","url":"https://alion.io/company/amd","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Jibe","truth_index":{"grade":"B","score":75,"open_postings":162,"ghost_share":0,"stale_share":0.994,"repost_share":0,"time_to_fill_p50_days":29,"computed_at":"2026-10-26T05:57:25Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Cork, Ireland"],"countries":["IE"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":112000,"max_usd":236000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":646},"experience_years_min":7,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Formal Verification","optional":false},{"name":"UVM","optional":false},{"name":"Perl","optional":true},{"name":"Python","optional":true},{"name":"Ruby","optional":true},{"name":"SystemVerilog","optional":true}],"status":"live","first_seen_at":"2026-10-05T14:53:00Z","employer_posted_date":"2026-10-20","last_verified_at":"2026-10-26T13:33:26Z","board_verified":true,"closed_at":null,"days_open":21,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":21},"description":"ADVANCE YOUR CAREER. ADVANCE THE WORLD.\nAt AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.\nWhether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Join us and, together, we’ll advance your career.\nSr. STAFF/STAFF SILICON DESIGN ENGINEER (PCIe)\n\nTHE ROLE:\nAMD is looking for an experienced Design Verification Engineer willing to take on the challenge of verifying a leading edge PCIe Controller Sub-System Design. In this role you will be given an opportunity to work on the next generation Power optimization technology that will be part of future AMD SOCs powering AI Training and Inference, Gaming Consoles, Servers and Personal Computers as well as Graphics Cards and VR sets. This team is responsible for the Verification of several critical blocks, interoperability of lower level IPs and the SubSystem delivery to SoC. The team is tasked with verifying a balanced architecture between power consumption and performance, delivering high complexity RTL code and Verification components, as well as creating advanced testbenches using leading-edge verification techniques.\nLOCATION:\n\nPrimary - Cork\nSecondary - Dublin\nTHE PERSON:\nA successful candidate will work with architects and fellow design and verification leads. The candidate will be highly accurate and detail-oriented, possessing strong communication, mentoring, leadership and problem-solving skills. Can work well with cross functional teams. Skilled at driving team and tasks from start to completion with superior quality. Drives to learn and perform at his or her highest potential in a technical capacity. Flexible in working hours to accommodate working with co-workers in different time-zones.\nKEY RESPONSIBILITIES:\nWork on PCIe Controller verification execution from test plan to verification signoff.\nCollaborate with architects and designers to understand the IP features.\nWrite/Implement/Review Test Plans.\nVerification of critical high speed digital designs using both coverage driven random and directed testing techniques as well as Formal verification.\nOwn some or all aspects of the Verification flow from initial test planning to coverage convergence and sign-off closure for one or more features and aspects of SubSystem level IP interoperability.\nBuild testbench components and develop test and sequence libraries, by applying Objected Oriented Programming Verification techniques following UVM methodology.\nConduct and participate in Code Reviews.\nTechnical leadership, including block ownership from start to finish and verification sign-off.\nPREFERRED EXPERIENCE:\nExperience with Low Power verification techniques and UPF flow is highly desirable \nPC System Architecture: PCI Express, SATA, USB, Ethernet, HyperTransport, DDR. Excellent knowledge of standard bus/interface protocols (i.e., AXI, AHB, AMBA, OCP, PIPE).\nExposure to AI implementation to improve verification flows\nExperience with simulation profiling, efficiency improvements, acceleration, HLS tools/process.\nMust be a self-starter, and able to drive independently and efficiently challenge time-critical tasks to on-time completion.\nStrong communication, time management, and presentation skills.\nScripting language experience: Perl, Ruby, Makefile, shell preferred.\nProven experience in verifying commercially successful IPs, Subsystems and or SoCs.\nStrong ability to provide mentorship and guidance to junior and senior engineers, a very effective team player, must have strong technical skills and provide a positive influence on team morale and culture.\nMust be expert in SystemVerilog, UVM.\nProficient in object-oriented programming, scripting (Ruby, Python, Perl), and low-level programming languages.\nACADEMIC CREDENTIALS:\nBachelors or Masters degree in Electronics/Computer/Electrical Engineering with 7+ years of relevant DV experience \nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.\nSr. STAFF/STAFF SILICON DESIGN ENGINEER (PCIe)\n\nTHE ROLE:\nAMD is looking for an experienced Design Verification Engineer willing to take on the challenge of verifying a leading edge PCIe Controller Sub-System Design. In this role you will be given an opportunity to work on the next generation Power optimization technology that will be part of future AMD SOCs powering AI Training and Inference, Gaming Consoles, Servers and Personal Computers as well as Graphics Cards and VR sets. This team is responsible for the Verification of several critical blocks, interoperability of lower level IPs and the SubSystem delivery to SoC. The team is tasked with verifying a balanced architecture between power consumption and performance, delivering high complexity RTL code and Verification components, as well as creating advanced testbenches using leading-edge verification techniques.\nLOCATION:\n\nPrimary - Cork\nSecondary - Dublin\nTHE PERSON:\nA successful candidate will work with architects and fellow design and verification leads. The candidate will be highly accurate and detail-oriented, possessing strong communication, mentoring, leadership and problem-solving skills. Can work well with cross functional teams. Skilled at driving team and tasks from start to completion with superior quality. Drives to learn and perform at his or her highest potential in a technical capacity. Flexible in working hours to accommodate working with co-workers in different time-zones.\nKEY RESPONSIBILITIES:\nWork on PCIe Controller verification execution from test plan to verification signoff.\nCollaborate with architects and designers to understand the IP features.\nWrite/Implement/Review Test Plans.\nVerification of critical high speed digital designs using both coverage driven random and directed testing techniques as well as Formal verification.\nOwn some or all aspects of the Verification flow from initial test planning to coverage convergence and sign-off closure for one or more features and aspects of SubSystem level IP interoperability.\nBuild testbench components and develop test and sequence libraries, by applying Objected Oriented Programming Verification techniques following UVM methodology.\nConduct and participate in Code Reviews.\nTechnical leadership, including block ownership from start to finish and verification sign-off.\nPREFERRED EXPERIENCE:\nExperience with Low Power verification techniques and UPF flow is highly desirable \nPC System Architecture: PCI Express, SATA, USB, Ethernet, HyperTransport, DDR. Excellent knowledge of standard bus/interface protocols (i.e., AXI, AHB, AMBA, OCP, PIPE).\nExposure to AI implementation to improve verification flows\nExperience with simulation profiling, efficiency improvements, acceleration, HLS tools/process.\nMust be a self-starter, and able to drive independently and efficiently challenge time-critical tasks to on-time completion.\nStrong communication, time management, and presentation skills.\nScripting language experience: Perl, Ruby, Makefile, shell preferred.\nProven experience in verifying commercially successful IPs, Subsystems and or SoCs.\nStrong ability to provide mentorship and guidance to junior and senior engineers, a very effective team player, must have strong technical skills and provide a positive influence on team morale and culture.\nMust be expert in SystemVerilog, UVM.\nProficient in object-oriented programming, scripting (Ruby, Python, Perl), and low-level programming languages.\nACADEMIC CREDENTIALS:\nBachelors or Masters degree in Electronics/Computer/Electrical Engineering with 7+ years of relevant DV experience \nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.","description_format":"text","description_chars":9666,"description_truncated":false,"requirements":{"experience_years_min":7,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Computer Components","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-10-20T09:28:01Z"}],"visa":[],"liveness":{"score":45,"band":"ok","label":"Likely open","p_open":1,"p_active":0.604,"p_room":0.75,"age_days":20,"expected_fill_days":29,"reasons":["conf:1","stale_co","velocity","win:late","comp:brand"],"computed_at":"2026-10-26T05:57:25Z"},"pay":null,"html_url":"https://alion.io/job/amd-sr-staffstaff-silicon-design-engineer-pcie","json_url":"https://alion.io/job/amd-sr-staffstaff-silicon-design-engineer-pcie.json","meta":{"generated_at":"2026-10-26T16:48:51Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":22578,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-27T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":93},"rest":"https://alion.io/mcp/rest/get_company?id=93"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Famd-sr-staffstaff-silicon-design-engineer-pcie"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Famd-sr-staffstaff-silicon-design-engineer-pcie"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Famd-sr-staffstaff-silicon-design-engineer-pcie"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/amd-sr-staffstaff-silicon-design-engineer-pcie\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Famd-sr-staffstaff-silicon-design-engineer-pcie"}]}