{"id":2911356,"url":"https://alion.io/job/amd-sram-circuit-design-engineer","title":"SRAM Circuit Design Engineer","company":{"id":93,"name":"AMD","domain":"amd.com","url":"https://alion.io/company/amd","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Jibe","truth_index":{"grade":"B","score":80,"open_postings":157,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":15,"computed_at":"2026-10-22T06:10:10Z"}},"role":"Hardware","role_family":"Hardware","seniority":null,"employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Boxborough, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":112000,"max_usd":253000,"period":"year","method":"role_country_seniority_unknown","sample_n":2844},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":true},{"name":"Python","optional":true},{"name":"Verilog","optional":true}],"status":"live","first_seen_at":"2026-09-04T20:46:00Z","employer_posted_date":"2026-10-20","last_verified_at":"2026-10-22T19:30:57Z","board_verified":true,"closed_at":null,"days_open":48,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":48},"description":"ADVANCE YOUR CAREER. ADVANCE THE WORLD.\nAt AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them.\nAMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger - technology that moves the world forward.\nTHE ROLE:\nAMD’s Cores Organization develops the CPU cores and cache technologies that power next-generation server, client, and gaming products. We are seeking an experienced Physical Design Engineer to help drive the implementation of high-performance SRAM and memory structures that are fundamental to modern CPU architectures. In this role, you will contribute to the design and optimization of performance-critical SRAM and memory structures within AMD processor cores. You will collaborate closely with architecture, RTL, circuit design, and physical design teams to deliver solutions that balance performance, power, area, and schedule. Direct exposure to SRAM design and memory-centric implementation challenges is highly valued for this position.\nTHE PERSON:\nThe ideal candidate has strong analytical thinking and problem-solving skills and exceptional attention to detail. We work on programs with long development cycles, so self-motivation and a commitment to meeting deadlines is required. We are pushing the envelope on chip performance, so the status quo must be challenged on every program. This requires creativity and innovation, but also excellent verbal and written communication skills. We work in small teams, but we are part of a large cross-site Cores organization, so teamwork is also vital to our success.\nKEY RESPONSIBILITIES:\nContribute to the physical design and implementation of high-speed SRAM and memory structures for advanced CPU products.\nWork closely with architecture, RTL, circuit design, and physical design teams to optimize power, performance, area, and schedule.\nPerform floorplanning, placement, clock tree synthesis, routing, timing closure, and design optimization activities.\nAnalyze and resolve implementation, timing, power, and signoff challenges.\nDevelop creative solutions to complex design and tool-related problems.\nContribute to methodology and flow improvements that increase design quality and efficiency.\nCreate and deliver technical presentations, design reviews, and documentation for engineering teams and management.\nSupport physical verification, extraction, reliability analysis, and design signoff activities.\n\nPREFERRED EXPERIENCE:\nExperience with high-speed SRAM design, memory design, or memory-centric physical implementation.\nStrong understanding of CPU, cache, or other performance-critical digital designs.\nStrong understanding of computer architecture, hardware design concepts, and performance, power, and area tradeoffs.\nKnowledge of chip-level floorplanning, bus and pin planning, clock tree synthesis, placement, optimization, routing, and timing closure.\nExperience with parasitic extraction, static timing analysis, physical verification, and design signoff methodologies.\nFamiliarity with power integrity analysis, including IR-drop and electromigration.\nAbility to comprehend complex Verilog RTL and make modifications to support timing, power, or implementation objectives.\nKnowledge of digital circuits, including high-speed flops, synchronizers, level shifters, and SRAM.\nExperience using industry-standard EDA tools for physical design and implementation.\nFamiliarity with scripting or programming languages such as Tcl, Perl, C, Python, or similar.\nACADEMIC CREDENTIALS:\nBachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field preferred.\n\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.\nTHE ROLE:\nAMD’s Cores Organization develops the CPU cores and cache technologies that power next-generation server, client, and gaming products. We are seeking an experienced Physical Design Engineer to help drive the implementation of high-performance SRAM and memory structures that are fundamental to modern CPU architectures. In this role, you will contribute to the design and optimization of performance-critical SRAM and memory structures within AMD processor cores. You will collaborate closely with architecture, RTL, circuit design, and physical design teams to deliver solutions that balance performance, power, area, and schedule. Direct exposure to SRAM design and memory-centric implementation challenges is highly valued for this position.\nTHE PERSON:\nThe ideal candidate has strong analytical thinking and problem-solving skills and exceptional attention to detail. We work on programs with long development cycles, so self-motivation and a commitment to meeting deadlines is required. We are pushing the envelope on chip performance, so the status quo must be challenged on every program. This requires creativity and innovation, but also excellent verbal and written communication skills. We work in small teams, but we are part of a large cross-site Cores organization, so teamwork is also vital to our success.\nKEY RESPONSIBILITIES:\nContribute to the physical design and implementation of high-speed SRAM and memory structures for advanced CPU products.\nWork closely with architecture, RTL, circuit design, and physical design teams to optimize power, performance, area, and schedule.\nPerform floorplanning, placement, clock tree synthesis, routing, timing closure, and design optimization activities.\nAnalyze and resolve implementation, timing, power, and signoff challenges.\nDevelop creative solutions to complex design and tool-related problems.\nContribute to methodology and flow improvements that increase design quality and efficiency.\nCreate and deliver technical presentations, design reviews, and documentation for engineering teams and management.\nSupport physical verification, extraction, reliability analysis, and design signoff activities.\n\nPREFERRED EXPERIENCE:\nExperience with high-speed SRAM design, memory design, or memory-centric physical implementation.\nStrong understanding of CPU, cache, or other performance-critical digital designs.\nStrong understanding of computer architecture, hardware design concepts, and performance, power, and area tradeoffs.\nKnowledge of chip-level floorplanning, bus and pin planning, clock tree synthesis, placement, optimization, routing, and timing closure.\nExperience with parasitic extraction, static timing analysis, physical verification, and design signoff methodologies.\nFamiliarity with power integrity analysis, including IR-drop and electromigration.\nAbility to comprehend complex Verilog RTL and make modifications to support timing, power, or implementation objectives.\nKnowledge of digital circuits, including high-speed flops, synchronizers, level shifters, and SRAM.\nExperience using industry-standard EDA tools for physical design and implementation.\nFamiliarity with scripting or programming languages such as Tcl, Perl, C, Python, or similar.\nACADEMIC CREDENTIALS:\nBachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field preferred.\n\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.","description_format":"text","description_chars":9414,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Electrical & Electronic Engineering","Processors, MCUs & AI Chips","Computer Components","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-10-20T09:36:36Z"}],"visa":[],"liveness":{"score":7,"band":"cold","label":"Long shot","p_open":1,"p_active":0.21,"p_room":0.35,"age_days":47,"expected_fill_days":15,"reasons":["conf:1","stale_co","velocity","win:tail","comp:brand"],"computed_at":"2026-10-22T06:10:10Z"},"pay":null,"html_url":"https://alion.io/job/amd-sram-circuit-design-engineer","json_url":"https://alion.io/job/amd-sram-circuit-design-engineer.json","meta":{"generated_at":"2026-10-22T23:07:20Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":8630,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-23T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":93},"rest":"https://alion.io/mcp/rest/get_company?id=93"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Famd-sram-circuit-design-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Famd-sram-circuit-design-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Famd-sram-circuit-design-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/amd-sram-circuit-design-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Famd-sram-circuit-design-engineer"}]}