{"id":2910628,"url":"https://alion.io/job/amd-staconstraints-engineer","title":"STA/Constraints Engineer","company":{"id":93,"name":"AMD","domain":"amd.com","url":"https://alion.io/company/amd","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Jibe","truth_index":{"grade":"B","score":75,"open_postings":162,"ghost_share":0,"stale_share":0.994,"repost_share":0,"time_to_fill_p50_days":29,"computed_at":"2026-10-25T05:49:26Z"}},"role":"Hardware","role_family":"Hardware","seniority":null,"employment_type":null,"work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Vancouver, Canada"],"countries":["CA"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":71000,"max_usd":140000,"period":"year","method":"role_country_seniority_unknown","sample_n":146},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Shift-Left Security","optional":false},{"name":"Perl","optional":true},{"name":"Python","optional":true},{"name":"Verilog","optional":true}],"status":"live","first_seen_at":"2026-09-30T19:50:00Z","employer_posted_date":"2026-10-20","last_verified_at":"2026-10-25T09:43:52Z","board_verified":true,"closed_at":null,"days_open":24,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":24},"description":"ADVANCE YOUR CAREER. ADVANCE THE WORLD.\nAt AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.\nWhether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Join us and, together, we’ll advance your career.\n THE ROLE:\nThe STA/Constraints Engineer is responsible for developing FullChip constraints and timing closure. Person will work closely with Fellows, Principal Engineers, Architects, collaborate with cross functional worldwide teams across Physical Design, Timing Analysis, Synthesis, Physical Verification, Power signoff, and mentor/coach/guide Design Engineers.\nKEY RESPONSIBILITIES:\nOwn end-to-end delivery of designs (SOC and Sub-system integration) from timing constraints and timing signoff perspective.\nWork closely with the SOC Architecture team for SOC clocks & STA for statistical timing target goals.\nUnderstanding clock design requirements and making sure they are correctly set up in SDC.\nUnderstand timing margins (LVF/SSTA/Variations etc.) on the latest tech nodes and work with timing methodology teams for future and current projects.\nUnderstand design requirements, timelines and various milestones of a project and deliver FCT closure accordingly.\nCollaborate with CAD and EDA vendors to further strengthen AMD timing closure and constraints methodology. \nResponsible for cdc/lint, timing closure, lower power implementation and netlist quality check with RTL designer and PD team.\nWork on SDC development, STA (Static Timing) analysis, shift left of timing closure, CDC (Clock Domain Crossing).\nPREFERRED EXPERIENCE:\nIndustry experience in STA, constraints and timing signoff.\nExpert user of industry-standard PD tools like SNPS PT/GCA (must) and ICC2/FC (desired). \nGood experience with Perl/TCL/Shell/Python scripting, and Verilog RTL design.\nExcellent presentation and inter-communication skills.\nExperience with Verilog RTL design/implementation and has experience of large digital ASIC project.\nExperience with physical design is a plus.\nHas Synthesis or physical implement experience.\nExperience with lower power design methodology.\nGood English skills on talking, presentation and writing documents.\nGood communication and strong sense of responsibility, task scheduling, and time management.\nACADEMIC CREDENTIALS:\nBachelor/Master’s degree in Micro Electronics/ Integrated Circuit Science, or related field preferred.\nLOCATION: Vancouver, BC\n#LI-HYBRID\n#LI-PA1\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.\nTHE ROLE:\nThe STA/Constraints Engineer is responsible for developing FullChip constraints and timing closure. Person will work closely with Fellows, Principal Engineers, Architects, collaborate with cross functional worldwide teams across Physical Design, Timing Analysis, Synthesis, Physical Verification, Power signoff, and mentor/coach/guide Design Engineers.\nKEY RESPONSIBILITIES:\nOwn end-to-end delivery of designs (SOC and Sub-system integration) from timing constraints and timing signoff perspective.\nWork closely with the SOC Architecture team for SOC clocks & STA for statistical timing target goals.\nUnderstanding clock design requirements and making sure they are correctly set up in SDC.\nUnderstand timing margins (LVF/SSTA/Variations etc.) on the latest tech nodes and work with timing methodology teams for future and current projects.\nUnderstand design requirements, timelines and various milestones of a project and deliver FCT closure accordingly.\nCollaborate with CAD and EDA vendors to further strengthen AMD timing closure and constraints methodology. \nResponsible for cdc/lint, timing closure, lower power implementation and netlist quality check with RTL designer and PD team.\nWork on SDC development, STA (Static Timing) analysis, shift left of timing closure, CDC (Clock Domain Crossing).\nPREFERRED EXPERIENCE:\nIndustry experience in STA, constraints and timing signoff.\nExpert user of industry-standard PD tools like SNPS PT/GCA (must) and ICC2/FC (desired). \nGood experience with Perl/TCL/Shell/Python scripting, and Verilog RTL design.\nExcellent presentation and inter-communication skills.\nExperience with Verilog RTL design/implementation and has experience of large digital ASIC project.\nExperience with physical design is a plus.\nHas Synthesis or physical implement experience.\nExperience with lower power design methodology.\nGood English skills on talking, presentation and writing documents.\nGood communication and strong sense of responsibility, task scheduling, and time management.\nACADEMIC CREDENTIALS:\nBachelor/Master’s degree in Micro Electronics/ Integrated Circuit Science, or related field preferred.\nLOCATION: Vancouver, BC\n#LI-HYBRID\n#LI-PA1\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.","description_format":"text","description_chars":6835,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"master","optional":true},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[{"name":"Canada","iso":"CA","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Computer Components","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-10-20T09:28:01Z"}],"visa":[],"liveness":{"score":39,"band":"fade","label":"Fading","p_open":1,"p_active":0.52,"p_room":0.75,"age_days":24,"expected_fill_days":29,"reasons":["conf:0","stale_co","velocity","win:late","comp:brand"],"computed_at":"2026-10-25T05:49:26Z"},"pay":null,"html_url":"https://alion.io/job/amd-staconstraints-engineer","json_url":"https://alion.io/job/amd-staconstraints-engineer.json","meta":{"generated_at":"2026-10-25T10:59:22Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":15743,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-26T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":93},"rest":"https://alion.io/mcp/rest/get_company?id=93"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Famd-staconstraints-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Famd-staconstraints-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Famd-staconstraints-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/amd-staconstraints-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Famd-staconstraints-engineer"}]}