{"id":3449224,"url":"https://alion.io/job/amd-staff-engineer-serdes-verification","title":"Staff Engineer - SerDes Verification","company":{"id":93,"name":"AMD","domain":"amd.com","url":"https://alion.io/company/amd","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Jibe","truth_index":{"grade":"A","score":95,"open_postings":8,"ghost_share":0,"stale_share":0,"repost_share":0,"time_to_fill_p50_days":81,"computed_at":"2026-11-02T06:13:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Singapore"],"countries":["SG"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":81000,"max_usd":160000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":13},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Formal Verification","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verification & Validation","optional":false},{"name":"VHDL","optional":false},{"name":"Perl","optional":true},{"name":"Python","optional":true},{"name":"Verilog","optional":true}],"status":"live","first_seen_at":"2026-10-29T06:04:00Z","employer_posted_date":"2026-10-29","last_verified_at":"2026-11-02T16:06:30Z","board_verified":true,"closed_at":null,"days_open":4,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":4},"description":"ADVANCE YOUR CAREER. ADVANCE THE WORLD.\nAt AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.\nWhether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Join us and, together, we’ll advance your career.\nTHE ROLE:\nThe role involves building UVM/SystemVerilog testbenches, running simulations, debugging timing and protocol issues, and evaluating signal integrity, jitter, BER, and eye diagrams. Close collaboration with design and hardware teams ensures compliance with protocols such as UCIe, PCIe, and DDR, delivering reliable, high-performance silicon.\nTHE PERSON:\nAs aSerDes Verification Engineer, you will be responsible for the verification and validation of high-speed SerDes interfaces, including testing signal integrity, performance, and protocol compliance. You will work closely with hardware and design teams to ensure that SerDes designs meet the required specifications, operating parameters, and quality standards. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.\nKEY RESPONSIBILITIES:\n Verification of SerDes Designs:\nDevelop and execute verification plans and testbenches for SerDes IPs (Intellectual Property) and subsystems to ensure they meet functional and performance requirements. \nDrive formal verification for the block and write formal properties and assertions to verify the design. \nEstimate the time required to write the new feature tests and any required changes to the test environment. \nBuild the directed and random verification tests. \nReview functional and code coverage metrics - modify or add tests or constrain random tests to meet the coverage requirements\n Testbench Development: Design and implement verification testbenches using industry-standard verification methodologies (e.g., UVM, SystemVerilog, VHDL).\nSimulation and Debugging:\nPerform simulations, analyze results, and debug issues related to timing, protocol errors, and other design anomalies in SerDes blocks. \nDebug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues\n Performance Evaluation: Evaluate and validate performance characteristics of SerDes systems including jitter, bit error rates (BER), signal integrity, eye diagrams, and other key metrics.\nProtocol Compliance Testing: Verify adherence to relevant SerDes protocols such as UCIe, PCIe, Ethernet, USB, DDR, DisplayPort, or custom protocols.\nAutomated Testing: Develop automated regression tests to ensure the robustness and stability of the SerDes design over multiple versions and iterations.\nCollaboration: Work closely with the design, hardware, and software teams to troubleshoot issues, implement fixes, and verify design changes.\nDocumentation: Create detailed reports and documentation on verification results, test scenarios, and issues found during testing.\nContinuous Improvement: Provide feedback for design and verification process improvements and contribute to innovation in verification strategies and methodologies\nPREFERRED EXPERIENCE:\nExperience in SerDes verification or high-speed communication verification.\nStrong hands-on experience with verification methodologies such as UVM, SystemVerilog, or other simulation-based verification tools.\nKnowledge of high-speed serial protocols such as UCIe, PCIe, Ethernet, USB, DDR, or custom protocols.\nExperience in analyzing and interpreting signal integrity issues, jitter, BER, and eye diagrams.\nSolid understanding of SerDes architectures, link training, and equalization.\nStrong debugging skills, with the ability to work across multiple domains (timing, protocol, performance).\nFamiliarity with hardware description languages (HDL) like VHDL or Verilog.\nStrong analytical, problem-solving, and communication skills.\nExperience with DDR protocol (e.g., DDR3, DDR4, DDR5) for memory interface verification.\nUnderstanding of UCIe protocol and its role in chiplet-to-chiplet communication.\nExperience with Python, Perl, or similar scripting languages for automation.\nExposure to high-speed memory interface design and verification, including DDR controller IP verification.\nAbility to work in a fast-paced environment and manage multiple verification tasks.\nACADEMIC CREDENTIALS:\nBachelors or Masters degree in Computer Engineering/Electrical Engineering \nLOCATION:\n\nSingapore\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.\nTHE ROLE:\nThe role involves building UVM/SystemVerilog testbenches, running simulations, debugging timing and protocol issues, and evaluating signal integrity, jitter, BER, and eye diagrams. Close collaboration with design and hardware teams ensures compliance with protocols such as UCIe, PCIe, and DDR, delivering reliable, high-performance silicon.\nTHE PERSON:\nAs aSerDes Verification Engineer, you will be responsible for the verification and validation of high-speed SerDes interfaces, including testing signal integrity, performance, and protocol compliance. You will work closely with hardware and design teams to ensure that SerDes designs meet the required specifications, operating parameters, and quality standards. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.\nKEY RESPONSIBILITIES:\n Verification of SerDes Designs:\nDevelop and execute verification plans and testbenches for SerDes IPs (Intellectual Property) and subsystems to ensure they meet functional and performance requirements. \nDrive formal verification for the block and write formal properties and assertions to verify the design. \nEstimate the time required to write the new feature tests and any required changes to the test environment. \nBuild the directed and random verification tests. \nReview functional and code coverage metrics - modify or add tests or constrain random tests to meet the coverage requirements\n Testbench Development: Design and implement verification testbenches using industry-standard verification methodologies (e.g., UVM, SystemVerilog, VHDL).\nSimulation and Debugging:\nPerform simulations, analyze results, and debug issues related to timing, protocol errors, and other design anomalies in SerDes blocks. \nDebug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues\n Performance Evaluation: Evaluate and validate performance characteristics of SerDes systems including jitter, bit error rates (BER), signal integrity, eye diagrams, and other key metrics.\nProtocol Compliance Testing: Verify adherence to relevant SerDes protocols such as UCIe, PCIe, Ethernet, USB, DDR, DisplayPort, or custom protocols.\nAutomated Testing: Develop automated regression tests to ensure the robustness and stability of the SerDes design over multiple versions and iterations.\nCollaboration: Work closely with the design, hardware, and software teams to troubleshoot issues, implement fixes, and verify design changes.\nDocumentation: Create detailed reports and documentation on verification results, test scenarios, and issues found during testing.\nContinuous Improvement: Provide feedback for design and verification process improvements and contribute to innovation in verification strategies and methodologies\nPREFERRED EXPERIENCE:\nExperience in SerDes verification or high-speed communication verification.\nStrong hands-on experience with verification methodologies such as UVM, SystemVerilog, or other simulation-based verification tools.\nKnowledge of high-speed serial protocols such as UCIe, PCIe, Ethernet, USB, DDR, or custom protocols.\nExperience in analyzing and interpreting signal integrity issues, jitter, BER, and eye diagrams.\nSolid understanding of SerDes architectures, link training, and equalization.\nStrong debugging skills, with the ability to work across multiple domains (timing, protocol, performance).\nFamiliarity with hardware description languages (HDL) like VHDL or Verilog.\nStrong analytical, problem-solving, and communication skills.\nExperience with DDR protocol (e.g., DDR3, DDR4, DDR5) for memory interface verification.\nUnderstanding of UCIe protocol and its role in chiplet-to-chiplet communication.\nExperience with Python, Perl, or similar scripting languages for automation.\nExposure to high-speed memory interface design and verification, including DDR controller IP verification.\nAbility to work in a fast-paced environment and manage multiple verification tasks.\nACADEMIC CREDENTIALS:\nBachelors or Masters degree in Computer Engineering/Electrical Engineering \nLOCATION:\n\nSingapore\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. 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