{"id":2909886,"url":"https://alion.io/job/amd-staff-package-design-engineer","title":"Staff Package Design Engineer","company":{"id":93,"name":"AMD","domain":"amd.com","url":"https://alion.io/company/amd","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Jibe","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["George Town, Malaysia"],"countries":["MY"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":27000,"max_usd":56000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":601},"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Ansys HFSS","optional":true},{"name":"Ansys SIwave","optional":true},{"name":"Cadence Allegro","optional":true},{"name":"Cadence Sigrity","optional":true},{"name":"Keysight ADS","optional":true}],"status":"live","first_seen_at":"2026-10-19T09:06:00Z","employer_posted_date":"2026-10-20","last_verified_at":"2026-10-22T04:24:27Z","board_verified":true,"closed_at":null,"days_open":2,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":2},"description":"ADVANCE YOUR CAREER. ADVANCE THE WORLD.\nAt AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.\nWhether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Join us and, together, we’ll advance your career.\nTHE ROLE:\nWe are looking for a Senior or Staff Package Design Engineer to own the design of advanced IC packages from concept through tape-out and production. You will work with SoC, silicon, signal integrity, power integrity, thermal, and manufacturing teams. Your goal is to make sure our packages meet electrical, mechanical, thermal, and cost targets for high-speed interfaces such as LPDDR5X/LPDDR6, PCIe, and die-to-die links. You will also set design methodology and mentor other engineers. We have competitive benefit packages and an award-winning culture. Join us!\nTHE PERSON:\nAs a Staff Package Design Engineer, you will be responsible for the electrical, physical, and mechanical design of advanced semiconductor packages, ensuring optimal signal integrity, power integrity, and manufacturability. You will collaborate closely with cross-functional teams in silicon design, system architecture, signal/power integrity, substrate vendors, and assembly/test operations to deliver high-performance, cost-effective, and reliable package solutions for next-generation products.\nKEY RESPONSIBILITIES:\nExecute package substrate design from concept through production release, including floorplanning, routing, stack-up definition, and design rule validation.\nPartner with AMD architects, designers, and product owners to define high yielding, cost effective substrate solutions which meet product requirements\nDefine and implement package architecture based on product electrical, thermal, and mechanical requirements.\nWork with chip, board, and system teams to optimize I/O planning, bump/ball assignments, and interface signal integrity.\nConduct design feasibility studies and trade-off analysis for performance, cost, and reliability.\nDrive DFX (Design for Manufacturability, Assembly, and Test) into the package design process.\nPerform modelling extraction for signal integrity and power integrity analysis, including high-speed interfaces (DDR/LPDDR, PCIe, SerDes, die-to-die links) and PDN impedance. Close design issues through layout changes and stack-up tuning.\nCollaborate with signal integrity (SI), power integrity (PI), and thermal analysis teams to ensure robust performance across operating conditions.\nInterface with substrate suppliers to define design rules, stack-ups, and material selection.\nContribute to design automation and flow improvement, scripting, and methodology development for package design efficiency.\nPREFERRED EXPERIENCE:\n5-10 years of relevant experience in IC or package design, preferably in advanced flip-chip, SiP, PoP, or 2.5D/3D packaging.\nExperience with high-speed interfaces (LPDDR, PCIe, SerDes, HBM, etc.).\nStrong understanding of substrate design flows (Cadence APD/SIP, Allegro).\nExperience in bump/ball map planning, layer stack-up, and design rule management.\nFamiliarity with manufacturing constraints and materials (BT, ABF, coreless, etc.).\nExcellent problem-solving, communication, and cross-functional collaboration skills.\nSolid knowledge of signal integrity, power integrity fundamentals, and thermal considerations in package design is a plus. \nExperience with analysis tools such as Ansys HFSS/SIwave/Q3D, Cadence Sigrity, or Keysight ADS is a plus.\nBasic scripting ability (SKILL, etc.) for design automation is a plus.\nACADEMIC CREDENTIALS:\nBachelor’s or Master’s degree in Electrical Engineering, Mechanical Engineering, Materials Science, or related field.\nLOCATION:\nPenang, Malaysia\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.\nTHE ROLE:\nWe are looking for a Senior or Staff Package Design Engineer to own the design of advanced IC packages from concept through tape-out and production. You will work with SoC, silicon, signal integrity, power integrity, thermal, and manufacturing teams. Your goal is to make sure our packages meet electrical, mechanical, thermal, and cost targets for high-speed interfaces such as LPDDR5X/LPDDR6, PCIe, and die-to-die links. You will also set design methodology and mentor other engineers. We have competitive benefit packages and an award-winning culture. Join us!\nTHE PERSON:\nAs a Staff Package Design Engineer, you will be responsible for the electrical, physical, and mechanical design of advanced semiconductor packages, ensuring optimal signal integrity, power integrity, and manufacturability. You will collaborate closely with cross-functional teams in silicon design, system architecture, signal/power integrity, substrate vendors, and assembly/test operations to deliver high-performance, cost-effective, and reliable package solutions for next-generation products.\nKEY RESPONSIBILITIES:\nExecute package substrate design from concept through production release, including floorplanning, routing, stack-up definition, and design rule validation.\nPartner with AMD architects, designers, and product owners to define high yielding, cost effective substrate solutions which meet product requirements\nDefine and implement package architecture based on product electrical, thermal, and mechanical requirements.\nWork with chip, board, and system teams to optimize I/O planning, bump/ball assignments, and interface signal integrity.\nConduct design feasibility studies and trade-off analysis for performance, cost, and reliability.\nDrive DFX (Design for Manufacturability, Assembly, and Test) into the package design process.\nPerform modelling extraction for signal integrity and power integrity analysis, including high-speed interfaces (DDR/LPDDR, PCIe, SerDes, die-to-die links) and PDN impedance. Close design issues through layout changes and stack-up tuning.\nCollaborate with signal integrity (SI), power integrity (PI), and thermal analysis teams to ensure robust performance across operating conditions.\nInterface with substrate suppliers to define design rules, stack-ups, and material selection.\nContribute to design automation and flow improvement, scripting, and methodology development for package design efficiency.\nPREFERRED EXPERIENCE:\n5-10 years of relevant experience in IC or package design, preferably in advanced flip-chip, SiP, PoP, or 2.5D/3D packaging.\nExperience with high-speed interfaces (LPDDR, PCIe, SerDes, HBM, etc.).\nStrong understanding of substrate design flows (Cadence APD/SIP, Allegro).\nExperience in bump/ball map planning, layer stack-up, and design rule management.\nFamiliarity with manufacturing constraints and materials (BT, ABF, coreless, etc.).\nExcellent problem-solving, communication, and cross-functional collaboration skills.\nSolid knowledge of signal integrity, power integrity fundamentals, and thermal considerations in package design is a plus. \nExperience with analysis tools such as Ansys HFSS/SIwave/Q3D, Cadence Sigrity, or Keysight ADS is a plus.\nBasic scripting ability (SKILL, etc.) for design automation is a plus.\nACADEMIC CREDENTIALS:\nBachelor’s or Master’s degree in Electrical Engineering, Mechanical Engineering, Materials Science, or related field.\nLOCATION:\nPenang, Malaysia\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.","description_format":"text","description_chars":9366,"description_truncated":false,"requirements":{"experience_years_min":5,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[{"name":"Malaysia","iso":"MY","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Computer Components","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-10-20T09:19:33Z"}],"visa":[],"liveness":{"score":90,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.903,"p_room":1,"age_days":1,"expected_fill_days":15,"reasons":["conf:3","velocity","win:early","comp:brand"],"computed_at":"2026-10-21T05:46:15Z"},"pay":null,"html_url":"https://alion.io/job/amd-staff-package-design-engineer","json_url":"https://alion.io/job/amd-staff-package-design-engineer.json","meta":{"generated_at":"2026-10-22T04:36:43Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":5047,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-23T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":93},"rest":"https://alion.io/mcp/rest/get_company?id=93"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Famd-staff-package-design-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Famd-staff-package-design-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Famd-staff-package-design-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/amd-staff-package-design-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Famd-staff-package-design-engineer"}]}