{"id":3141090,"url":"https://alion.io/job/amd-staff-silicon-design-engineer-physical-design","title":"Staff Silicon Design Engineer – Physical Design","company":{"id":93,"name":"AMD","domain":"amd.com","url":"https://alion.io/company/amd","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Jibe","truth_index":{"grade":"B","score":75,"open_postings":162,"ghost_share":0,"stale_share":0.994,"repost_share":0,"time_to_fill_p50_days":29,"computed_at":"2026-10-25T05:49:26Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Singapore"],"countries":["SG"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":80000,"max_usd":158000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":12},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Agentic Workflows","optional":false},{"name":"AI Agents","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Siemens Calibre","optional":true},{"name":"Synopsys Fusion Compiler","optional":true},{"name":"Synopsys PrimeTime","optional":true},{"name":"Synopsys StarRC","optional":true}],"status":"live","first_seen_at":"2026-10-23T05:23:00Z","employer_posted_date":"2026-10-23","last_verified_at":"2026-10-25T13:31:37Z","board_verified":true,"closed_at":null,"days_open":2,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":2},"description":"ADVANCE YOUR CAREER. ADVANCE THE WORLD.\nAt AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.\nWhether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Join us and, together, we’ll advance your career.\nTHE ROLE\nJoin our Singapore silicon design team across PnR, STA and physical design integration, supporting the full lifecycle from design handoff to timing convergence, physical verification and signoff. Depending on experience, you may own blocks, subsystems, STA or higher-level integration. AI-assisted and agentic workflows are central to how we work, and you'll use them with automation and modern EDA tools to accelerate delivery and improve quality.\nTHE PERSON\nYou enjoy solving complex physical design problems and understanding how logic, timing, physical implementation, power, verification and integration interact. You combine strong engineering fundamentals with an automation-first, AI-centric mindset, using scripting and AI-assisted techniques to analyze design data, improve workflows and build reusable solutions. You are data-driven, own problems from analysis through closure, and apply sound engineering judgment to independently validate everything AI produces.\nKEY RESPONSIBILITIES\nOwn or contribute to RTL/netlist-to-GDS implementation: floorplanning, power planning, placement, CTS, routing, optimization, ECOs and closure. \nDrive timing closure through STA, constraints (SDC) debugging, interface timing analysis and ECO development. \nSupport hierarchical physical design and integration at block, subsystem and top level. \nResolve challenges in timing, congestion, clocking, power, area, signal integrity and physical verification. \nSupport signoff: STA, DRC/LVS, antenna, low-power checks and EM/IR. \nBuild reusable automation in Tcl, Python, Perl or shell. \nUse AI coding assistants and agentic tools to speed up run analysis, debug, scripting and workflow automation, and share what works across the team. Review and validate all AI output before relying on it. \nCollaborate with RTL, circuit, integration, CAD and global engineering teams.\nPREFERRED EXPERIENCE\nHands-on experience in one or more of: PnR, STA and timing closure, SDC development, physical design integration, physical verification and signoff, low-power design, EM/IR.\nSynopsys and/or Cadence tools, such as Fusion Compiler, Innovus, PrimeTime, Tempus, StarRC or Calibre.\nExperience debugging complex design or flow problems.\nAdvanced nodes and hierarchical designs are an advantage.\nExperience building reusable flows or methodologies is highly desirable.\nLOCATION\nSingapore\n#LI-D&I\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.\nTHE ROLE\nJoin our Singapore silicon design team across PnR, STA and physical design integration, supporting the full lifecycle from design handoff to timing convergence, physical verification and signoff. Depending on experience, you may own blocks, subsystems, STA or higher-level integration. AI-assisted and agentic workflows are central to how we work, and you'll use them with automation and modern EDA tools to accelerate delivery and improve quality.\nTHE PERSON\nYou enjoy solving complex physical design problems and understanding how logic, timing, physical implementation, power, verification and integration interact. You combine strong engineering fundamentals with an automation-first, AI-centric mindset, using scripting and AI-assisted techniques to analyze design data, improve workflows and build reusable solutions. You are data-driven, own problems from analysis through closure, and apply sound engineering judgment to independently validate everything AI produces.\nKEY RESPONSIBILITIES\nOwn or contribute to RTL/netlist-to-GDS implementation: floorplanning, power planning, placement, CTS, routing, optimization, ECOs and closure. \nDrive timing closure through STA, constraints (SDC) debugging, interface timing analysis and ECO development. \nSupport hierarchical physical design and integration at block, subsystem and top level. \nResolve challenges in timing, congestion, clocking, power, area, signal integrity and physical verification. \nSupport signoff: STA, DRC/LVS, antenna, low-power checks and EM/IR. \nBuild reusable automation in Tcl, Python, Perl or shell. \nUse AI coding assistants and agentic tools to speed up run analysis, debug, scripting and workflow automation, and share what works across the team. Review and validate all AI output before relying on it. \nCollaborate with RTL, circuit, integration, CAD and global engineering teams.\nPREFERRED EXPERIENCE\nHands-on experience in one or more of: PnR, STA and timing closure, SDC development, physical design integration, physical verification and signoff, low-power design, EM/IR.\nSynopsys and/or Cadence tools, such as Fusion Compiler, Innovus, PrimeTime, Tempus, StarRC or Calibre.\nExperience debugging complex design or flow problems.\nAdvanced nodes and hierarchical designs are an advantage.\nExperience building reusable flows or methodologies is highly desirable.\nLOCATION\nSingapore\n#LI-D&I\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.","description_format":"text","description_chars":7224,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Computer Components","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-10-23T08:30:41Z"}],"visa":[],"liveness":{"score":63,"band":"ok","label":"Likely open","p_open":1,"p_active":0.632,"p_room":1,"age_days":2,"expected_fill_days":29,"reasons":["conf:0","stale_co","velocity","win:early","comp:brand"],"computed_at":"2026-10-25T05:49:26Z"},"pay":null,"html_url":"https://alion.io/job/amd-staff-silicon-design-engineer-physical-design","json_url":"https://alion.io/job/amd-staff-silicon-design-engineer-physical-design.json","meta":{"generated_at":"2026-10-25T13:47:54Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":19724,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-26T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":93},"rest":"https://alion.io/mcp/rest/get_company?id=93"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Famd-staff-silicon-design-engineer-physical-design"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Famd-staff-silicon-design-engineer-physical-design"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Famd-staff-silicon-design-engineer-physical-design"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/amd-staff-silicon-design-engineer-physical-design\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Famd-staff-silicon-design-engineer-physical-design"}]}