{"id":2910798,"url":"https://alion.io/job/amd-technical-fellow-high-speed-interconnect-optics","title":"Technical Fellow - High-Speed Interconnect & Optics","company":{"id":93,"name":"AMD","domain":"amd.com","url":"https://alion.io/company/amd","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Jibe","truth_index":{"grade":"B","score":75,"open_postings":163,"ghost_share":0,"stale_share":0.994,"repost_share":0,"time_to_fill_p50_days":28,"computed_at":"2026-10-24T06:02:35Z"}},"role":"Science & Research","role_family":"Science & Research","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Santa Clara, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":108000,"max_usd":286000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":584},"experience_years_min":null,"visa_sponsorship":true,"relocation_package":false,"has_equity":false,"technologies":[{"name":"HPC","optional":false}],"status":"live","first_seen_at":"2026-09-23T18:02:00Z","employer_posted_date":"2026-10-20","last_verified_at":"2026-10-24T22:21:35Z","board_verified":true,"closed_at":null,"days_open":31,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":31},"description":"WHAT YOU DO AT AMD CHANGES EVERYTHING\nAt AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gamingand embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuityand a shared passion to create something extraordinary. When you join AMD, you’lldiscover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.Together, we advance your career.\nTHE ROLE:\nThe Technical Fellow for High-Speed Interconnect and Optics is a senior technical leader responsible for defining and advancing NTSG’s system-level interconnect architecture for next-generation AI, HPC, and data center platforms. This role drives innovation across electrical and optical interconnect technologies-spanning ASICs, advanced packaging, boards, optics, and full-system integration-while shaping industry direction and contributing to AMD’s long-term technology roadmap\nTHE PERSON:\nDefining next-generation interconnect architecture in this Lead role and long-term strategy for next-generation electrical and optical interconnects, including pluggable optics, co-packaged optics (CPO), co-packaged copper (CPC), and onboard optics (OBO), enabling scalable AI scale-up and scale-out system architectures.\nKEY RESPONSIBILITIES:\nDrive System-Level SI/PI Excellence\nProvide technical authority and leadership in high-speed signal integrity (SI) and power delivery network (PDN) design across ASICs, packages, boards, connectors, and optical interfaces. Ensure robust, end-to-end performance at 112G, 224G, and beyond under real-world system operating conditions.\nLead Optical System Integration and Packaging Innovation\nDrive end-to-end optical system integration, including optics module architecture, silicon photonics, laser integration (internal and external), advanced packaging solutions, and thermal and power optimization for high-density systems.\nGuide SerDes and ASIC Co-Optimization\nInfluence SerDes architecture, specifications, modeling assumptions, and tuning strategies to ensure alignment between ASIC design and real-world channel behavior, optical characteristics, packaging constraints, and system-level requirements.\nHands-On Technical Leadership and Debug\nServe as a hands-on technical authority during lab bring-up, characterization, and system debug. Resolve complex, cross-layer issues spanning SI/PI, optics, firmware, packaging, and system-level interactions across development and deployment phases.\nShape Industry Direction and Ecosystem Alignment\nRepresent AMD as a technical leader in industry standards bodies and consortia (e.g., OIF, IEEE, PCI-SIG). Influence next-generation specifications, drive ecosystem alignment, and ensure AMD’s interconnect roadmap leads and aligns with industry trends.\nMentor and Multiply Technical Impact\nMentor senior engineers, architects, and emerging technical leaders. Establish best practices, architectural frameworks, and design guidelines to elevate technical excellence across teams and business units.\nInfluence Business and Product Strategy\nAct as a trusted technical advisor to senior leadership. Drive critical technical trade-offs, vendor and partner strategy, and product go/no-go decisions that materially impact product direction, risk, cost, and time-to-market.\nPREFERRED QUALIFICATIONS:\nDeep expertise in high-speed signal integrity and power integrity (SI/PI, PDN) for advanced data rates (112G, 224G, and beyond).\nStrong experience across optical interconnect technologies, including:\nPluggable optics (QSFP, OSFP)\nCo-Packaged Optics (CPO)\nCo-Packaged Copper (CPC)\nOn-Board Optics (OBO)\nProven experience in optical packaging and system integration, including silicon photonics, laser coupling strategies, and thermal and power management at scale.\nHands-on experience with system bring-up, validation, and debug across ASICs, packages, boards, and optical subsystems.\nStrong understanding of SerDes architecture, equalization, FEC, and system-level channel modeling.\nDemonstrated ability to lead across organizational boundaries and influence vendors, partners, customers, and standards bodies.\nTrack record of sustained technical leadership and architectural impact across multiple product generations.\nRecognized industry or academic thought leader; publications and patents a strong plus\nACADEMIC CREDENTIALS:\nMaster’s in Computer Science, Electrical Engineering, Photonics, or a related technical field, PhD preferred\nLocation:\nSanta Clara, CA\nThis role is not eligible for visa sponsorship.\n#LI-RF1\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.\n\nThis posting is for an existing vacancy.\nTHE ROLE:\nThe Technical Fellow for High-Speed Interconnect and Optics is a senior technical leader responsible for defining and advancing NTSG’s system-level interconnect architecture for next-generation AI, HPC, and data center platforms. This role drives innovation across electrical and optical interconnect technologies-spanning ASICs, advanced packaging, boards, optics, and full-system integration-while shaping industry direction and contributing to AMD’s long-term technology roadmap\nTHE PERSON:\nDefining next-generation interconnect architecture in this Lead role and long-term strategy for next-generation electrical and optical interconnects, including pluggable optics, co-packaged optics (CPO), co-packaged copper (CPC), and onboard optics (OBO), enabling scalable AI scale-up and scale-out system architectures.\nKEY RESPONSIBILITIES:\nDrive System-Level SI/PI Excellence\nProvide technical authority and leadership in high-speed signal integrity (SI) and power delivery network (PDN) design across ASICs, packages, boards, connectors, and optical interfaces. Ensure robust, end-to-end performance at 112G, 224G, and beyond under real-world system operating conditions.\nLead Optical System Integration and Packaging Innovation\nDrive end-to-end optical system integration, including optics module architecture, silicon photonics, laser integration (internal and external), advanced packaging solutions, and thermal and power optimization for high-density systems.\nGuide SerDes and ASIC Co-Optimization\nInfluence SerDes architecture, specifications, modeling assumptions, and tuning strategies to ensure alignment between ASIC design and real-world channel behavior, optical characteristics, packaging constraints, and system-level requirements.\nHands-On Technical Leadership and Debug\nServe as a hands-on technical authority during lab bring-up, characterization, and system debug. Resolve complex, cross-layer issues spanning SI/PI, optics, firmware, packaging, and system-level interactions across development and deployment phases.\nShape Industry Direction and Ecosystem Alignment\nRepresent AMD as a technical leader in industry standards bodies and consortia (e.g., OIF, IEEE, PCI-SIG). Influence next-generation specifications, drive ecosystem alignment, and ensure AMD’s interconnect roadmap leads and aligns with industry trends.\nMentor and Multiply Technical Impact\nMentor senior engineers, architects, and emerging technical leaders. Establish best practices, architectural frameworks, and design guidelines to elevate technical excellence across teams and business units.\nInfluence Business and Product Strategy\nAct as a trusted technical advisor to senior leadership. Drive critical technical trade-offs, vendor and partner strategy, and product go/no-go decisions that materially impact product direction, risk, cost, and time-to-market.\nPREFERRED QUALIFICATIONS:\nDeep expertise in high-speed signal integrity and power integrity (SI/PI, PDN) for advanced data rates (112G, 224G, and beyond).\nStrong experience across optical interconnect technologies, including:\nPluggable optics (QSFP, OSFP)\nCo-Packaged Optics (CPO)\nCo-Packaged Copper (CPC)\nOn-Board Optics (OBO)\nProven experience in optical packaging and system integration, including silicon photonics, laser coupling strategies, and thermal and power management at scale.\nHands-on experience with system bring-up, validation, and debug across ASICs, packages, boards, and optical subsystems.\nStrong understanding of SerDes architecture, equalization, FEC, and system-level channel modeling.\nDemonstrated ability to lead across organizational boundaries and influence vendors, partners, customers, and standards bodies.\nTrack record of sustained technical leadership and architectural impact across multiple product generations.\nRecognized industry or academic thought leader; publications and patents a strong plus\nACADEMIC CREDENTIALS:\nMaster’s in Computer Science, Electrical Engineering, Photonics, or a related technical field, PhD preferred\nLocation:\nSanta Clara, CA\nThis role is not eligible for visa sponsorship.\n#LI-RF1\nBenefits offered are described: AMD benefits at a glance.\nAMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.\nAMD may use Artificial Intelligence to help screen, assess or select applicants for this position. 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